Filters








142,461 Hits in 4.9 sec

Synthesis of Sequential Reversible Circuits through Finite State Machine [article]

Shubham Gupta
2015 arXiv   pre-print
Our propose designs of reversible counters are significantly better in optimization parameters such as gate counts, garbage outputs and constant inputs available in literature.  ...  T flip-flop and hence designing low cost synchronous and asynchronous counters. Another side is to generate the circuit from its behavioral description described in FSM form.  ...  In 4 - 4 bit synchronous Up/ Down counter, the two operations (Up and Down) can be combined in one circuit. This counter can be capable of counting either up or down [32].  ... 
arXiv:1410.2370v3 fatcat:cnxml765tjhahoaesdtphrgrcq

Improved synthesis of reversible sequential circuits

Mozammel H A Khan, Jacqueline E. Rice
2016 2016 IEEE International Symposium on Circuits and Systems (ISCAS)  
Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using emerging technologies such as quantum dot cellular automata.  ...  This work is an improved version of our direct feedback method, which uses a different approach to the reversible mapping of sequential circuits.  ...  EXAMPLE 1: 4-BIT UP/DOWN COUNTER In this section we illustrate our technique by designing a four-bit falling-edge trigged up/down counter with asynchronous loading.  ... 
doi:10.1109/iscas.2016.7539044 dblp:conf/iscas/KhanR16b fatcat:u4gat2bjmzfoljouvvfnlqc6r4

A Low Power VLSI Design of an All Digital Phase Locked Loop
English

Nakkina Vydehi, A . S Srinivasa Rao
2014 International Journal of Engineering Trends and Technoloy  
This work Implements an ADPLL with Nyquist rate phase detector which is basically a digital multiplier, simulation results proves a very high speed of operation for low frequency ranges and resource utilization  ...  Sateesh Kumar, Head of the ECE Department of Aditya institute of technology and management for their encouragement and support in bringing out this paper.  ...  I am grateful to all Teaching members of the department for their valuable suggestions and encouragement. The authors sincerely acknowledge the contributions made by other team members.  ... 
doi:10.14445/22315381/ijett-v16p256 fatcat:viluw6ajlvcvtdgofx32lkxm4q

Synchronous up/down binary counter for LUT FPGAs with counting frequency independent of counter size

Alexandre F. Tenca, Miloš D. Ercegovac
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
This paper presents the design of a fast up/down binary counter for LUT FPGAs. The counter has a cycle time independent of the counter size.  ...  Experimental results show that the counter can scale up to hundreds of bits while keeping a short cycle time.  ...  We improve the functionality of the counter making it an up/down counter.  ... 
doi:10.1145/258305.258334 dblp:conf/fpga/TencaE97 fatcat:jgx5ei3jkzd5zet6h63lrdi5zu

Pyrrolyl-, 2-(2-thienyl)pyrrolyl- and 2,5-bis(2-thienyl)pyrrolyl-nucleosides: synthesis, molecular and electronic structure, and redox behaviour of C5-thymidine derivatives

Miguel A. Galindo, Jennifer Hannant, Ross W. Harrington, William Clegg, Benjamin R. Horrocks, Andrew R. Pike, Andrew Houlton
2011 Organic and biomolecular chemistry  
The molecular structure of compound 7 (Figure 4) , the tpt-derivative with a C 5 chain, reveals an up-up-down arrangement of the heteroatoms, though again there is some disorder in the thienyl S1-ring  ...  In the N2-containing independent molecule, the hetero atoms show an up-up-down arrangement and a more coplanar arrangement, with thienyl-pyrrolyl interplanar angles of 33.2° and 31.1°.  ...  In the molecular structure of 5, the three heterocyclic rings are oriented such that the hetero atoms alternate in an up-down-up arrangement (Figure 2) .  ... 
doi:10.1039/c0ob00466a pmid:21240418 fatcat:3z34on253zcnhl6tmwpzkpq4wu

Design an All Digital PLL with Ripple Reduction Technique

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
This paper presents an all digital approach for the design, simulation, synthesis and implementation of FPGA based ADPLL centered at 195.31 KHz using Verilog HDL code.  ...  Ripple reduction technique reduces the use of Kth counter, Kth counter comes under consideration when enable is ON. Phase locked loops are most widely used in communication system.  ...  The Kth up/down counter consists of one reference clock, up and down counter, and at the output it gives carry and borrow.  ... 
doi:10.35940/ijitee.j9518.0881019 fatcat:t4ifosarvvhafhf7nuggw2e7aa

Understanding Tool Synthesis Behavior and Safe Finite State Machine Design [article]

Katie Liszewski, Timothy McDonley
2021 arXiv   pre-print
In this work the default behavior of three synthesis tools interacting with high reliability FSMs is discussed.  ...  Post-synthesis netlists of test FSMs are analyzed for optimization induced changes that affect reliability during a SEU. Best practices are proposed to curtail aggressive optimizers.  ...  The FSM includes a count up or down option to provide some complexity but is always held at count up for testing. The default case is a transition back to state 0.  ... 
arXiv:2108.04042v1 fatcat:f447liq6afcc7naicnckle677y

Page 462 of Cellular and Molecular Life Sciences Vol. 49, Issue 5 [page]

1993 Cellular and Molecular Life Sciences  
Furthermore TNFx down- regulates the IL-1 receptor in chondrocytes” and in- duces or stimulates the synthesis of the IL-1 receptor antagonist in neutrophils and the synthesis of G-CSF and GM-CSF in macrophages  ...  Also, the induction of IL-1 on one hand and the synthesis of IL-1RA, or the down-regula- tion of IL-1R on the other hand, could be possible ways of keeping processes balanced in the cytokine network.  ... 

Portable digital clock generator for digital signal processing applications

T. Olsson, P. Nilsson
2003 Electronics Letters  
A free-running ring oscillator is used as internal clock and the output clock is generated using two counters.  ...  The clock generator is described in synthesisable VHDL-code and can therefore easily be made from standard cells found in any commercial standard CMOS cell library.  ...  Synthesis and layout: The clock generator was synthesised and verified using post-synthesis simulations using a multiplication factor of 10 for both a 0.35 mm 3.3 V and a 0.18 mm 1.8 V CMOS technology.  ... 
doi:10.1049/el:20030910 fatcat:ypa4vvdffjft7f37z5psgp2wem

Mathematical Model of Heavy Duty Welded Plate Heat Exchanger and its Validation in Industry

L.L. Tovazhnyanskyy, P.O. Kapustenko, O.Y. Perevertaylenko, O.P. Arsenyeva, P.Y. Arsenyev
2017 Chemical Engineering Transactions  
The construction of investigated WPHE is developed for work in high pressure shell of ammonia synthesis column at pressure up to 32 MPa and temperature up to 520 °C.  ...  The use of WPHE instead shell-and-tube unit enable to cut down the volume occupied by heat exchanger in high pressure shell of ammonia synthesis column and allows increase of the volume of catalyst.  ...  Acknowledgments The support of Grant of Education and Science Ministry of the Republic Kazakhstan in state program "Grant funding for research", for sub priority:" Power and machine building (Heat and  ... 
doi:10.3303/cet1761245 doaj:f5546ed27cce4789954b1bfec34a5ecc fatcat:e2cb3c7wibf3dhohuf6dfnbkrm

Careful Autonomous Agents in Environments With Multiple Common Resources

Rodica Condurache, Catalin Dima, Madalina Jitaru, Youssouf Oualhadj, Nicolas Troquard
2022 Electronic Proceedings in Theoretical Computer Science  
Careful rational synthesis was defined in (Condurache et al. 2021) as a quantitative extension of Fisman et al.'  ...  We thus explore the problem of careful rational synthesis with several resources. We show that the problem is undecidable.  ...  Given a transition δ , we note g i [lo] the lower-bound for counter i and g i [up] the upper-bound.  ... 
doi:10.4204/eptcs.362.3 fatcat:s5qpdk4jy5havk5cvwxpqugrna

An Effective Programmable Memory BIST for Embedded Memory

Youngkyu PARK, Jaeseok PARK, Taewoo HAN, Sungho KANG
2009 IEICE transactions on information and systems  
This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms.  ...  Finally, various and complex algorithms can be run thanks to its support of multi-loop. key words: Programmable BIST, test algorithm, multi-loop  ...  Acknowledgments This work was supported by "System IC 2010" project of Korea Ministry of Knowledge Economy.  ... 
doi:10.1587/transinf.e92.d.2508 fatcat:ck67ndgm35bspdydg2fil4msum

Subthreshold Frequency Synthesis for Medical Implantable Transceivers [chapter]

Tarek Khan, Kaamran Raahemifar
2011 Biomedical Engineering, Trends in Electronics, Communications and Software  
Transient simulations of the 6-bit and 7-bit programmable counters were performed to verify the desired behaviour of the down counters.  ...  The DMP divides CLK IN by (M + 1) until the swallow counter has counted down to 0.  ... 
doi:10.5772/14234 fatcat:3ofl6ma35zh4xaruvkkowazkqi

Stability measurements of microwave frequency synthesis with liquid helium cooled cryogenic sapphire oscillators [article]

J.G. Hartnett, D.L. Creedon, D. Chambon, G. Santarelli
2010 arXiv   pre-print
We report on the evaluation of microwave frequency synthesis using two cryogenic sapphire oscillators developed at the University of Western Australia.  ...  A down converter is used to make comparisons between microwave clocks at different frequencies, where the synthesized signal has a stability not significantly different from the reference oscillator.  ...  The cable FIG. 7: Block diagram of the down conversion synthesis to 100 MHz from 11.200386 GHz of CSO1 and the up conversion to 11.200000 GHz, via 45 m of LMR-195 coax and the 56th harmonic of a second  ... 
arXiv:1004.0775v1 fatcat:apsdidlaffdcllk3ftq2vgtgza

Stability measurements of frequency synthesis with cryogenic sapphire oscillators

John G. Hartnett, Daniel Creedon, D. Chambon, G. Santarelli
2009 2009 IEEE International Frequency Control Symposium Joint with the 22nd European Frequency and Time forum  
We report on the evaluation of microwave frequency synthesis using two cryogenic sapphire oscillators developed at the University of Western Australia.  ...  A down converter is used to make comparisons between microwave clocks at different frequencies, where the synthesized signal has a stability not significantly different from the reference oscillator.  ...  The cable FIG. 7: Block diagram of the down conversion synthesis to 100 MHz from 11.200386 GHz of CSO1 and the up conversion to 11.200000 GHz, via 45 m of LMR-195 coax and the 56th harmonic of a second  ... 
doi:10.1109/freq.2009.5168203 fatcat:ohghdld6vjcj5ddyjidix2m4ia
« Previous Showing results 1 — 15 out of 142,461 results