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Synthesis of Fault Attacks on Cryptographic Implementations

Gilles Barthe, François Dupressoir, Pierre-Alain Fouque, Benjamin Grégoire, Jean-Christophe Zapalowicz
2014 Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security - CCS '14  
Using a specialized form of program synthesis, we discover multiple faulted implementations on RSA and ECDSA that realize the fault conditions, and hence lead to fault attacks.  ...  We propose, implement, and evaluate a new approach for finding fault attacks against cryptographic implementations.  ...  a form of program synthesis on concrete cryptographic implementations to automatically discover faulted implementations that realize fault conditions and lead to attacks.  ... 
doi:10.1145/2660267.2660304 dblp:conf/ccs/BartheDFGZ14 fatcat:umeubeeravaivdu7iklul5unca

An EDA tool for implementation of low power and secure crypto-chips

Behnam Ghavami, Hossein Pedram, Mehrdad Najibi
2009 Computers & electrical engineering  
Regarding the significant mathematical immunity of recent cryptographic algorithms, attacks considering the physical aspects of these algorithms, known as side channel attacks, have received much of interest  ...  However, due to lack of automatic synthesis and optimization tools for these circuits, implementation of secure asynchronous circuits encounters many difficulties.  ...  implementation of a cryptographic algorithm.  ... 
doi:10.1016/j.compeleceng.2008.06.014 fatcat:3bjrexmnbvbilme54efiw64hni

Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography

L. Breveglieri, I. Koren
2006 IEEE transactions on computers  
Moreover, attacks on crypto-systems based on malicious injection of faults (for the purpose of extracting the secret key) have unfortunately proven to be very successful, making their own security another  ...  The high complexity of such implementations makes reliability a challenge.  ...  This paper demonstrates the mathematical complexity of studying fault attacks on cryptographic systems. The second paper, "Combining Crypto with Biometrics Effectively" by F. Hao, R. Anderson, and J.  ... 
doi:10.1109/tc.2006.149 fatcat:zdfs3ihjxfehdlycpzjpfbc5ra

Design and Implementation of Low Power AES SBOX with Error Detection Circuit

V. Devendiran, S. Letitia
2015 Research Journal of Applied Sciences Engineering and Technology  
The objective of the study is to detect the error using parity bit for the AES SBOX and implementation in hardware with low area and power.  ...  This circuit can products the AES Encryption/Decryption process and systems against fault based attacks. It can also apply to any digital communication systems and security related applications.  ...  Unlike direct attacks on the algorithm, these techniques, called Side Channel Attacks, attempt to gather knowledge of sensitive data that may leak from a particular implementation of the cryptographic  ... 
doi:10.19026/rjaset.10.2436 fatcat:lltl4gpc2naqjeg6fus62k44ty

Countermeasure against fault sensitivity analysis based on clock check block

Jinbao Zhang, Ning Wu, Fen Ge, Fang Zhou, Xiaoqing Zhang
2018 IEICE Electronics Express  
Fault sensitivity analysis (FSA), as a new type of fault attacks, has been proved a serious threat to the security of cryptographic circuits.  ...  We first design a clock check block (CCB) to detect the fault clock which is necessary for carrying on FSA, and then design an enable signal module to change the output of the cryptographic circuit once  ...  Fault attack [2, 3] , as one of the wellknown physical attacks, which exploits the faulty outputs to crack the key of cryptographic modules, has became a serious threaten to the security of cryptographic  ... 
doi:10.1587/elex.15.20180433 fatcat:2gmxpfzkhvf7pfwknp2wn3f5ea

A cryptography core tolerant to DFA fault attacks

Carlos Roberto Moratelli, Ï Cota, Marcelo Soares Lubaszewski
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
This kind of attack is a real threat to tamper resistant devices like Smart Cards. To tackle such attacks, the cryptographic core must be immune to transient faults.  ...  Furthermore, the proposed solution is independent of implementation, and can be applied to other cryptographic algorithms, such as AES.  ...  Luigi Carro for valuable discussions on the subject.  ... 
doi:10.1145/1150343.1150393 dblp:conf/sbcci/MoratelliCL06 fatcat:oqabgjroingu7noaxo6y4gfq5u

Fault injection test bed for clock violation or metastability based Cipher attacks on FPGA hardware

Rashmi Singh
2013 IOSR Journal of VLSI and Signal processing  
The encryption module output with faults introduced and without fault introduced is compared as a function of ratio of used clock frequency and maximum frequency of operation reported by synthesis tool  ...  The UART interface is realized on FPGA to provide PC based controlling for this fault injection.  ...  It allows us to examine an FPGA-based circuit, in particular an implementation of a cryptographic algorithm, subjected to a fault injection attack based on clock glitching.  ... 
doi:10.9790/4200-0333843 fatcat:xbk4q2dkbfbi3kbmccuth7wz3m

Cryptographic Fault Diagnosis using VerFI

Victor Arribas, Felix Wegener, Amir Moradi, Svetla Nikova
2020 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)  
Here, we introduce the concept of Cryptographic Fault Diagnosis, which revises and shapes the notions of fault diagnosis in reliability testing to the needs of evaluating cryptographic implementations.  ...  Among several case studies, we demonstrate its application on an implementation of LED cipher with combined countermeasures against side-channel analysis and fault-injection attacks (published at CRYPTO  ...  Evaluation The primary goal of designing VerFI is to verify countermeasures against fault attacks on cryptographic implementations.  ... 
doi:10.1109/host45689.2020.9300264 fatcat:w3z6atxubrc6rcmbtgzaepqgue

Side-channel power analysis of different protection schemes against fault attacks on AES

Pei Luo, Yunsi Fei, Liwei Zhang, A. Adam Ding
2014 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)  
We implement six different schemes and launch correlation power analysis attacks on them.  ...  A protection circuit can be added into cryptographic systems to detect both soft errors and injected faults required by Differential Fault Analysis (DFA) attacks.  ...  Such addition may incur extra power leakages in cryptographic systems, which means while designing a scheme for protecting against a given attack (fault injection attacks), the implemented countermeasure  ... 
doi:10.1109/reconfig.2014.7032555 dblp:conf/reconfig/LuoFZD14 fatcat:jkkjrwqjjfbzvpgi4ajstcutxa

Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults

G. Gaubatz, E. Savas, B. Sunar
2008 IEEE transactions on computers  
In the relatively young field of fault-tolerant cryptography, the main research effort has focused exclusively on the protection of the data path of cryptographic circuits.  ...  We introduce a metric that measures the effectiveness of the error detection technique in terms of the effort the attacker has to make in relation to the area overhead spent in implementing the EDC.  ...  Erkay Savaş is supported by the Scientific and Technological Research Council of Turkey Project 105E089.  ... 
doi:10.1109/tc.2007.70784 fatcat:l5mtnidjandobaaxq7ustrcixq

Proving SIFA Protection of Masked Redundant Circuits [article]

Vedad Hadzic, Robert Primas, Roderick Bloem
2021 arXiv   pre-print
Implementation attacks like side-channel and fault attacks pose a considerable threat to cryptographic devices that are physically accessible by an attacker.  ...  We implemented this new method in a tool called Danira, which can show the SIFA resistance of cryptographic implementations like AES S-Boxes within minutes.  ...  Redundant computation is an implementation-level fault attack countermeasure for cryptographic computations.  ... 
arXiv:2107.01917v1 fatcat:wwnahrywhfatrp5cfxwa3zr65q

An AOP-Based Security Verification Environment for KECCAK Hash燗lgorithm

Hassen Mestiri, Imen Barraj, Mohsen Machhout
2022 Computers Materials & Continua  
At the ESL, we discuss a unique technique for simulating security fault attacks on cryptographic systems.  ...  Robustness of the electronic cryptographic devices against fault injection attacks is a great concern to ensure security.  ...  Fault injection attacks are one of the most effective forms of attacks against electronic cryptographic systems.  ... 
doi:10.32604/cmc.2022.029794 fatcat:4fxcgaukr5d5vpu6agkiyswvli

Reset Tree-Based Optical Fault Detection

Dong-Geon Lee, Dooho Choi, Jungtaek Seo, Howon Kim
2013 Sensors  
As one of the most powerful invasive attacks on cryptographic hardware, optical fault attacks cause semiconductors to misbehave by injecting high-energy light into a decapped integrated circuit.  ...  In this paper, we present a new reset tree-based scheme to protect cryptographic hardware against optical fault injection attacks.  ...  Introduction Fault injection is one of the most threatening types of attack, revealing information in a cryptographic integrated circuit (IC) by causing chip malfunction.  ... 
doi:10.3390/s130506713 pmid:23698267 pmcid:PMC3690077 fatcat:bjasrq4rtvemhaoytk6gkrbwfm

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks [chapter]

Konrad Kulikowski, Alexander Smirnov, Alexander Taubin
2006 Lecture Notes in Computer Science  
An implementation of the Advanced Encryption Standard based on these balanced cells and synthesized using our tool flow shows a 6.6 times throughput improvement over the synchronous automatically pipelined  ...  Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks.  ...  We recently discovered a new Combined Differential Power Analysis/Fault Injection (DPA/FI) attacks (or power attacks on faulty hardware) [31] .  ... 
doi:10.1007/11894063_31 fatcat:v7mshto3evbfrc55vgumhsqvvu

Fault Injection Test Bed for Clock Violation

E. Kavitha, P.S. Indrani, M. J. C. Prasad
2013 International Journal of Computer Applications Technology and Research  
The encryption output with faults introduced and without faults introduced is compared as a function of ratio of used clock frequency and maximum frequency of operation reported by synthesis tool.  ...  The UART interface is realized on FPGA to provide PC based controlling for this fault injection. Xilinx chip scope tools will be used for verifying the output at various levels in FPGA hardware.  ...  It allows us to examine an FPGA-based circuit, in particular an implementation of a cryptographic algorithm, subjected to a fault injection attack based on clock glitching [7].  ... 
doi:10.7753/ijcatr0206.1020 fatcat:mkjwppyh25afdhmqseesyabbxm
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