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Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator

R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernandez, A. Rodriguez-Vazquez
2006 2006 IFIP International Conference on Very Large Scale Integration  
This paper presents the design of a continuous-time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems.  ...  The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation.  ...  ΣΔM and must be included in the synthesis methodology to obtain a functional modulator with minimum number of inter-stage paths.  ... 
doi:10.1109/vlsisoc.2006.313245 dblp:conf/vlsi/NavasARFR06 fatcat:lydu5a7hbvezflocjlwdwp5xqm

Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators

Ramón Tortosa, Rafael Castro-López, J.M. de la Rosa, Elisenda Roca, Ángel Rodríguez-Vázque, F.V. Fernández
2008 ETRI Journal  
Ramón Tortosa et al. 535 This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigmadelta (ΣΔ) modulators  ...  The design methodology described in this paper tries to reduce this design gap for a class of circuits, namely, continuous-time (CT) cascade sigma-delta (ΣΔ) modulators (conceptually shown in Fig. 1 ),  ...  Fig. 1 . 1 Conceptual block diagram of a cascade CT ΣΔ modulator. Fig. 2 . 2 Synthesis procedure. Fig. 3 . 3 Jitter vs. sampling frequency for a third-order CT ΣΔ modulator.  ... 
doi:10.4218/etrij.08.0107.0225 fatcat:qh27mj7yejcklj2flidw6vcnpa

Tools For Automated Design of ΣΔ Modulators [chapter]

F. Medeiro, J. M. de la Rosa, B. Pérez-Verdú, A. Rodríguez-Vázquez
2001 Analog Circuit Design  
We present a set of CAD tools to design ΣΔ modulators.  ...  We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a 8bit@1.26MHz central freq@10kHz bandwidth band-pass modulator.  ...  Fig. 10 . 10 (a) 4th-order two-stage SC ΣΔ modulator.  ... 
doi:10.1007/978-1-4613-1443-1_12 fatcat:qjhjcp5gyjhidhlrkffdzfjwna

Third-order Single-bit Sigma Delta modulator structure for an RF reception chain for a LTE network

2018 Australian Journal of Basic and Applied Sciences  
The Continuous-time (CT) structure becomes more advantageous compared to the disceret -time (DT) due to important properties such as implicit anti-aliasing, resistive input impedance and low power operation  ...  This paper presents a third-order Sigma Delta modulator for a LTE receiver. LTE is the latest Mobile Telecommunications technology being currently in development and testing phase.  ...  The LP ΣΔ modulators use the integrator as a loop filter, but the BP ΣΔ use resonators. Therefore, analysis and synthesis are the same only difference is the nature of filter.  ... 
doi:10.22587/ajbas.2018.12.7.2 fatcat:7neroqnjhjamppo6sjhqvvpbam

Design and Characterization of a 5.2 GHz/2.4 GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance

John W. M. Rogers, Foster F. Dai, Calvin Plett, Mark S. Cavin
2006 EURASIP Journal on Wireless Communications and Networking  
This paper presents a complete noise analysis of a ΣΔ-based fractional-N phase-locked loop (PLL) based frequency synthesizer.  ...  Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was 0.50 • rms and 0.535 • rms, respectively.  ...  Qing and Z. Zhou for layout support. This work would also not have been possible without the support of Dave Rahn.  ... 
doi:10.1155/wcn/2006/48489 fatcat:vlo7ap2prvcove7x35frm46s3e

Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages

J. Gerardo Garcia-Sanchez, Jose M. de la Rosa
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
modulators, more power efficient than hybrid monorate architectures and more robust than cascade continuous-time implementations. The combination of these features results in a new class of !"  ...  This paper presents novel architectures of multirate hybrid cascade continuous-time/discrete-time !"  ...  of Innovation, Science and Enterprise under contract TIC-2532.  ... 
doi:10.1109/iscas.2010.5537116 dblp:conf/iscas/Garcia-SanchezR10 fatcat:lh4blsulsndsplhb3xc3dqj3ly

A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS

Sohail Asghar, Rocio del Rio, Jose M. de la Rosa
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
This paper describes the design of a switched-capacitor fourth-order single-loop Σ∆ modulator with a 5-level embedded quantizer.  ...  The loop filter consists of a cascade of resonators with distributed feedforward (CRFF) coefficients, which can be programmed to make the zeros of the noise transfer function variable.  ...  Indeed, the modulator can be visualized as a cascade of two resonators.  ... 
doi:10.1109/vlsi-soc.2012.6379004 dblp:conf/vlsi/AsgharRR12 fatcat:ooekbu3m2rasdjt4h5l25sv2ce

Finite-Time Current Tracking in Boost Converters by Using a Saturated Super-Twisting Algorithm

Juan-Eduardo Velázquez-Velázquez, Rosalba Galván-Guerra, José-Antonio Ortega-Pérez, Yair Lozano-Hernández, Raúl Villafuerte-Segura, Ning Cai
2020 Complexity  
Besides, the controller is compared with a first-order sliding mode controller showing that for small sample times, the energy of the error signal is reduced.  ...  The proposed approach generates a continuous bounded control signal applied to the converter by using a sigma-delta modulator Σ Δ M .  ...  Acknowledgments In memory of Oscar Villafuerte-Segura, my brother, my partner, and unconditional friend. I will never forget you, Andrés A.  ... 
doi:10.1155/2020/7326157 fatcat:rsjcmskhczfnjo2tusemg55fpm

Band-pass ΣΔ architectures with single and two parallel paths

Herve Caracciolo, Ivano Galdi, Edoardo Bonizzoni, Franco Maloberti
2008 2008 IEEE International Symposium on Circuits and Systems  
This paper studies two different approaches: the use of resonators and the synthesis of the noise transfer function (NTF) starting from a closer function.  ...  The design strategies for band-pass modulators are discussed.  ...  In portable applications, band-pass modulators [1] are preferable because of their low power consumption either in continuous-time and sampled-data implementations.  ... 
doi:10.1109/iscas.2008.4541753 dblp:conf/iscas/CaraccioloGBM08 fatcat:55lbpkmryjholp6gmwqhe7vsya

DC stability analysis of high-order, lowpass ΣΔ modulators with distinct unit circle NTF zeros

Ngai Wong, Tung-Sang Ng
2003 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
continuous-time trajectories for modulators of arbitrary orders.  ...  It has been shown that a high-order modulator system can be decomposed into second-and first-order subsystems, thus facilitating graphical interpretation and analysis.  ... 
doi:10.1109/tcsii.2003.808901 fatcat:w5u6j33a5rdvrpfvi5l6qynssu

High Speed On-Chip Signal Generation for Debug and Diagnosis

Tsung-Yen Tsai, Sadok Aouini, Gordon Walter Roberts
2012 Journal of electronic testing  
A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to  ...  In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency).  ...  Custom PLL Design In order to test frequency and phase synthesis at high speeds, a custom PLL had to be designed and built.  ... 
doi:10.1007/s10836-012-5289-0 fatcat:xhv3vr7vqrdwtoijger26eeq7m

A Mixed-Signal Embedded Platform for Automotive Sensor Conditioning

Emilio Volpi, Luca Fanucci, Adolfo Giambastiani, Alessandro Rocchi, Francesco D'Ascoli, Marco Tonarelli, Massimiliano Melani, Corrado Marino
2010 EURASIP Journal on Embedded Systems  
Such platform consists in a wide set of optimized high-performance analog, digital, and software intellectual property (IP) modules for various kinds of sensors.  ...  Final ASIC implementation for the given sensor conditioning can be easily derived with reduced risk and short development time.  ...  Capacitive [42] acceleration/digital charge amplifier, Sample&Hold, comparator, ΣΔ modulator Capacitive  ... 
doi:10.1155/2010/945646 fatcat:yvl6wdkn5bdjvknha7d4trhfkq

FPGA based conducted EMI reduction using Randomized Multistage Sigma Delta

M. Joe Marshell, R Vimala, Aravind Britto
2021 Dynamic systems and applications  
This proposed (RMSDMD) PWM wave generation modules are implemented on an Alter a FPGA device using Quartus II synthesis software tool.  ...  Experimental results depict the considerable improvement in the conducted noise spectrum and the noise level was effectively reduced in the range of 9dBμV over other PWM Modulator.  ...  It can be like: • Cascaded Integrator Comb channels, regularly utilized for against associating during interjection and demolition activity which may modify the example pace of a framework with discrete-time  ... 
doi:10.46719/dsa202130.10.04 fatcat:bmtii7osfja7zgrhftg5gbhfca

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Jingcheng Zhuang, Robert Bogdan Staszewski
2014 IPSJ Transactions on System LSI Design Methodology  
It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation.  ...  The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection  ...  regular sinusoidal shape as generated by the crystal oscillator (XO) but it is more complex and requires either continuous-time operation or oversampling of the continuous-time reference  ... 
doi:10.2197/ipsjtsldm.7.2 fatcat:bmxnktjcfbgzxowua7jdgv5bx4

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI July 2020 2317-2330 Network synthesis Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis.  ...  ., +, TCSI Sept. 2020 3138-3151 Network analysis Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis.  ...  ., +, TCSI Feb. 2020 634-646 Histograms Linearity Theory of Stochastic Phase-Interpolation Time-to-Digital Converter. Gammoh, K., +,  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri
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