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Synthesis and Quantitative Verification of Tradeoff Spaces for Families of Software Systems [chapter]

Javier Cámara, David Garlan, Bradley Schmerl
2017 Lecture Notes in Computer Science  
Architectural styles [23] characterize the design space of families of software systems in terms of patterns of structural organization, defining a vocabulary of component and connector types, as well  ...  The main contribution of this paper is a formal framework for specification-driven synthesis and analysis of design spaces that provides formal guarantees about the correctness of system behaviors and  ...  The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the  ... 
doi:10.1007/978-3-319-65831-5_1 fatcat:67bfzlpgubhhfbo5gzoy2xww7q

Towards a Methodology for the Quantitative Evaluation of Automotive Architectures

Patrick Popp, Marco di Natale, Paolo Giusto, Sri Kanajan, Claudio Pinello
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents a system level architecture design methodology that is supported by tools and methods for the quantitative evaluation of key metrics of interest related to timing, dependability and  ...  Traditional approaches relying on component-level design and analysis are no longer effective as they do not always allow for the quantitative evaluation of properties arising from the composition of subsystems  ...  For timing related metrics and use cases (end to end latency verification, bus/cpu utilization, etc.), we propose the use of schedulability analysis theory and system-level simulation to provide formal  ... 
doi:10.1109/date.2007.364643 dblp:conf/date/PoppNGKP07 fatcat:3ecs4tugsrbzlj4g6s4dbjbabu

Formal and Informal Methods for Multi-Core Design Space Exploration

Jean-Francois Kempf, Olivier Lebeltel, Oded Maler
2014 Electronic Proceedings in Theoretical Computer Science  
We propose a tool-supported methodology for design-space exploration for embedded systems.  ...  We argue that this extension of the scope of formal verification is important for the viability of the domain.  ...  analysis/synthesis [16, 11] consists of decorating transition systems with numerical costs and tracking their evolution.  ... 
doi:10.4204/eptcs.154.6 fatcat:4urjwajsjnfnxnuxqhswam77im

The 2019 Comparison of Tools for the Analysis of Quantitative Formal Models [chapter]

Ernst Moritz Hahn, Arnd Hartmanns, Christian Hensel, Michaela Klauck, Joachim Klein, Jan Křetínský, David Parker, Tim Quatmann, Enno Ruijters, Marcel Steinmetz
2019 Msphere  
In this paper, we report on the challenges in setting up a quantitative verification competition, present the results of QComp 2019, summarise the lessons learned, and provide an outlook on the features  ...  QComp draws its benchmarks from the new Quantitative Verification Benchmark Set.  ...  Introduction Classic verification is concerned with functional, qualitative properties of models of systems or software: Can this assertion ever be violated?  ... 
doi:10.1007/978-3-030-17502-3_5 fatcat:33o3wyfdlvbb5cwqc7npqalml4

A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems

Omar Hammami, Zhoukun Wang, Virginie Fresse, Dominique Houzet
2008 EURASIP Journal on Embedded Systems  
In this paper, we conduct through a case study an evaluation of C-based design of embedded systems and point out the impact of behavioral synthesis on embedded systems multiobjective high-level partitioning  ...  Embedded systems require a high-level abstraction modeling to tackle their complexity and improve design productivity. Cbased design techniques and methodologies have been proposed for this purpose.  ...  ACKNOWLEDGMENT The authors are grateful to the reviewers for their excellent reviews which helped improve the paper dramatically.  ... 
doi:10.1155/2008/685128 fatcat:rljnxyocbzckxdfv23xmb27moy

Synthesis from Formal Partial Abstractions [article]

Hamid Bagheri
2014 arXiv   pre-print
frameworks from application architectures; and (3) synthesizing object-relational mapping tradeoff spaces and database schemas for database-backed object-oriented applications.  ...  However, it remains unreasonably difficult to build the modeling languages and translators required for software synthesis.  ...  This chapter discusses how this form of formal synthesis of tradeoff spaces can create valuable opportunities for novel forms of trade space analysis.  ... 
arXiv:1411.0481v1 fatcat:fi6qwflzlzdcvp35kfqky7wgru

Rethinking Digital Design: Why Design Must Change

Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz
2010 IEEE Micro  
At the system level, this observation is driving the recent push for parallel computing.  ...  Years of research have taught us that the best-and perhaps only-way to save energy is to cut waste.  ...  Acknowledgments We acknowledge the support of the  ... 
doi:10.1109/mm.2010.81 fatcat:5owcw4wum5cvpdd76jaxvpx4ly

Synthesis of probabilistic models for quality-of-service software engineering

Simos Gerasimou, Radu Calinescu, Giordano Tamburrelli
2018 Automated Software Engineering : An International Journal  
An increasingly used method for the engineering of software systems with strict quality-of-service (QoS) requirements involves the synthesis and verification of probabilistic models for many alternative  ...  EvoChecker can be used to synthesise the Pareto-optimal set of probabilistic models associated with the QoS requirements of a system under design, and to support the selection of a suitable system architecture  ...  , and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.  ... 
doi:10.1007/s10515-018-0235-8 fatcat:wnup7zmo2bfb7kgwiu6g3mfwsq

Low maintenance verification

Valeria Bertacco
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
Our ultimate vision for these technologies is to make hardware as malleable as software.  ...  While the past few decades have witnessed significant efforts to improve verification methodology for hardware systems, these efforts have been far outstripped by the massive complexity of modern digital  ...  languages [5] , [6] , [7] , and coverage analysis tools that provide a quantitative evaluation of the progress of verification [3] .  ... 
doi:10.1145/1150343.1150347 dblp:conf/sbcci/Bertacco06a fatcat:g7l2sxlwfvg5jbqolcvezk6orm

An Adaptive Design Methodology for Reduction of Product Development Risk

Hara Gopal Mani Pakala, Varaprasad, Raju, Ibrahim Khan
2011 International Journal of Ad Hoc, Sensor and Ubiquitous Computing  
However, product uncertainty is highest during early stages of development. Design verification is an essential step in the development of any system, especially for Embedded System.  ...  The back-bone of this frame-work is the development of Domain Specific Operational (DOP) Model and the associated Verification Instrumentation for Test and Evaluation, developed based on the DOP model.  ...  It consists of a compiler for synchronous program language Quartz, a symbolic model checker, and a tool for hardware and/or software synthesis.  ... 
doi:10.5121/ijasuc.2011.2303 fatcat:vxn5ijy6v5evhhzbntkxj2x63e

Toward a System Design Science [chapter]

Joseph Sifakis
2014 Lecture Notes in Computer Science  
It is an essential area of human experience, expertise, and knowledge, which deals with our ability to mold our environment to satisfy material and spiritual needs.  ...  One is simply a plan or a pattern for assembling objects constituting a given artifact. The other is the creative process for devising plans or patterns and carrying them out to produce an artifact.  ...  Peter Denning and Richard Snodgrass contributed to significantly improving the paper through constructive comments and criticism.  ... 
doi:10.1007/978-3-642-54848-2_15 fatcat:4g2ky252ezfdlihl7ig7xbteze

ASC: a stream compiler for computing with FPGAs

O. Mencer
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
ASC simplifies design-space exploration of hardware accelerators by transforming the hardware-design task into a software-design process, using only "GNU compiler collection (GCC)" and "make" to obtain  ...  From experience, the hardware-design productivity and ease of use are close to pure software development.  ...  A key element in DEFACTO is the use of synthesis estimation techniques, possibly from behavioral synthesis tools [22] , to quantitatively evaluate alternative designs for a loop nest computation.  ... 
doi:10.1109/tcad.2005.857377 fatcat:4ccpxhmrijgcfg4cwqo6kiry6a

Platform-based design and software design methodology for embedded systems

A. Sangiovanni-Vincentelli, G. Martin
2001 IEEE Design & Test of Computers  
under the direction of Richard Newton. 3 Cadence Research Laboratories and the System-Level Design Group have also heavily invested in these areas.  ...  Acknowledgments The two areas of investigation presented here constitute the main research lines of the System-Level Design effort at the Gigascale Silicon Research Center-a large, multisite research project  ...  In the design space, there is an obvious tradeoff between the API's abstraction level and the number and diversity of platform instances covered.  ... 
doi:10.1109/54.970421 fatcat:sml4bys7zff25m2pqmzws2vmq4

Reducing power in high-performance microprocessors

Vivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel, Franklin Baez
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described.  ...  The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling.  ...  ACKNOWLEDGMENTS The authors would like to thank Shekhar Borkar, Ricardo Suarez, Guy Therenin, Michael Walz, Steve Gunther, Shishpal Rawat and Jeff Parkhurst for assistance in writing this paper.  ... 
doi:10.1145/277044.277227 dblp:conf/dac/TiwariSRMPB98 fatcat:4vcawegsyveclg7uv42qgeffdy

A Survey of Challenges for Runtime Verification from Advanced Application Domains (Beyond Software) [article]

César Sánchez and Gerardo Schneider and Wolfgang Ahrendt and Ezio Bartocci and Domenico Bianculli and Christian Colombo and Yliés Falcone and Adrian Francalanza and Sran Krstić and Joa̋o M. Lourenço and Dejan Nickovic and Gordon J. Pace and Jose Rufino and Julien Signoles and Dmitriy Traytel and Alexander Weiss
2018 arXiv   pre-print
Most of the applications in runtime verification have been focused on the dynamic analysis of software, even though there are many more potential applications to other computational devices and target  ...  Other activities involve the instrumentation of the system to generate the trace and the communication between the system under analysis and the monitor.  ...  The authors would like to thank Fonenantsoa Maurica and Pablo Picazo-Sanchez for their feedback on parts of a preliminary version of this document.  ... 
arXiv:1811.06740v1 fatcat:4bxx5tvfpzez3jidsj22flibv4
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