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Improving the performance of an FPGA based Model design for sensor monitoring using PlanAhead tool
2006
2006 IEEE International Behavioral Modeling and Simulation Workshop
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The study in this paper is focused on the improvement of a Field Programmable Gate Arrays (FPGA) based design using a hierarchical analysis tool offered by XILINX PlanAhead'TM. ...
Verilog HDL has been used to develop and implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and framing. ...
path. 3-Dividing large hierarchical block into smaller RTL units to avoid the possibility of having long paths, which makes the floorplan a difficult task. ...
doi:10.1109/bmas.2006.283476
fatcat:nhusx43q2jffraf7ijvyn4iw6i
Hierarchical reconfiguration of FPGAs
2014
2014 24th International Conference on Field Programmable Logic and Applications (FPL)
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For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and ...
A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to ...
CONCLUSIONS In this paper, we introduced hierarchical reconfiguration of FPGAs which significantly reduces design complexity, FPGA resource requirements, and bitstream storage requirements for large systems ...
doi:10.1109/fpl.2014.6927491
dblp:conf/fpl/KochB14
fatcat:t2q2jjhlgna5zbo7nqgn3vkipq
Designing for Xilinx XC6200 FPGAs
[chapter]
1998
Lecture Notes in Computer Science
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With the XC6200 FPGA Xilinx introduced the first commercially available FPGA designed for reconfigurable computing. ...
Cells have nearest neighbor connections to their North, South, East and West neighbors. The device has a hierarchical busing scheme. ...
This is largely due to the advanced FPGA to CPU interface. The design philosophy appears to have been driven by the desire to produce a FPGA optimized for reconfigurable computing. ...
doi:10.1007/bfb0055230
fatcat:ibipiab5zvauleqwprdava6ihy
Performance driven floorplanning for FPGA based designs
1997
Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97
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Increasing design densities on large FPGAs and greater demand for performance, has called for special purpose tools like oorplanner, performance driven router, and more. ...
These methods are especially suitable for mapping designs on very large FPGAs. ...
VI Conclusions In this work we h a v e presented a methodology for hierarchical oorplanning and placement for large FPGA based designs. ...
doi:10.1145/258305.258321
dblp:conf/fpga/ShiB97
fatcat:hq4a4iszjvavph4wp7n3d2ehla
Innovate or perish
2004
Proceedings of the 2004 international symposium on Physical design - ISPD '04
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We will show that several well researched problems in the ASIC world need new problem formulations and algorithms research to be useful for today 's FPGAs. ...
The size and complexity of modern FPGAs has far outpaced the innovations in FPGA physical design. ...
Early Estimation and Analysis tools
Physical Synthesis Hierarchical design flows entail partitioning the design into smaller and more manageable pieces, apportioning temporal (timing budgeting) and physical ...
doi:10.1145/981066.981099
dblp:conf/ispd/TaghaviGRRS04
fatcat:gm6jrbwxbfbhnks4pyyu3svrpe
Partitioning of VLSI circuits and systems
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
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Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning problems to be solved on all levels of abstraction. ...
However, the optimal floorplan largely depends on the quality of the partitioning. ...
For parallel simulation and load balancing a hierarchical four-phase algorithm based on corolla clustering has been developed [46, 41] . ...
doi:10.1145/240518.240535
dblp:conf/dac/Johannes96
fatcat:wdgj4exw4zfw5mmaygdmlwwwmy
Frontier: A Fast Placement System for FPGAS
[chapter]
2000
IFIP Advances in Information and Communication Technology
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For a collection of large reconfigurable computing benchmark circuits our placement system exhibits a 4× speedup in combined place and route time versus commercial FPGA CAD software with improved design ...
It is shown that floorplanning, routability evaluation, and back-end optimization are all necessary to achieve efficient placement solutions. ...
While macro-blocks have been leveraged successfully for FPGA synthesis for some time, little work has been done in integrating macro techniques into automated FPGA layout. ...
doi:10.1007/978-0-387-35498-9_12
fatcat:wpq57c5itfalzotsvstr5476s4
FPGA Architectural Flow: CAD Improvements
2021
International Journal of Computer Applications
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This paper would be useful for new ASIC developers entering in the FPGA world, or even experienced FPGA developers who can get some ideas from this paper for the betterment of the FPGA compilation process ...
We will also do a brief comparison of ASIC vs FPGA design flow and FPGA architecture, connect the dots and make user better aware of the challenges that are faced by FPGA designers in implementing a certain ...
However, when it comes to very large and complex SoC where there are many complex core and peripheral logic and functionalities, then a hierarchical flow becomes a must. ...
doi:10.5120/ijca2021921054
fatcat:xaxxhgvawzfkfeoul2ajf4cjgq
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC
2021
ACM Symposium on Applied Computing
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The tool leverages mathematical optimization to solve the partitioning and floorplanning problems, and relies on a set of auto-generated scripts that interact with the vendor tools to mobilize the synthesis ...
The tool targets the Zynq 7-series and Ultrascale+ FPGA-based SoCs by Xilinx. ...
(ii) Floorplanning: Floorplanning involves the generation of physical placements for the RRs on the FPGA fabric. ...
doi:10.1145/3412841.3441928
dblp:conf/sac/SeyoumPBB21
fatcat:fwfcfq276vgsjowgqbftkeabvy
Fast placement approaches for FPGAs
2002
ACM Transactions on Design Automation of Electronic Systems
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For a collection of large reconfigurable computing benchmark circuits our timing-driven placement system exhibits a 2.6× speedup in combined place and route time versus commercial FPGA CAD software with ...
Next, FPGA routability and performance metrics are used to evaluate the quality of the initial placement. ...
While macro-blocks have been leveraged successfully for FPGA synthesis for some time, little work has been done in integrating macro techniques into automated FPGA layout. ...
doi:10.1145/544536.544540
fatcat:mrhqqwrt7vcy7kcyu3l4hzcutm
Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays
2010
2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers
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FPXAs are abstract structures that can be targeted for implementation on applicationspecific integrated circuits, FPGAs, or other kinds of reconfigurable processors. ...
In this paper, we introduce the concept of field programmable X arrays (FPXAs) as an abstract model for design and implementation of heterogeneous multiprocessor arrays for signal processing systems. ...
National Science Foundation under Awards 0720536, 0720596, 0823989, and 0824040. ...
doi:10.1109/acssc.2010.5757924
fatcat:cuz2mwonnfcpbp5jvvc6a3qkkq
Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices
2008
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications ...
Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. ...
In this paper, synthesis tools are used to create both ASIC and heterogeneous FPGA implementations of algorithms in order to evaluate the performance gains of ASIC over FPGA. ...
doi:10.1109/tvlsi.2008.2000259
fatcat:ctw7ativojh7zei63zt7bqnt2e
Proceedings of the ASP-DAC 2003. Asia and South Pacific Design Automation Conference 2003 (Cat. No.03EX627)
2003
Conference of Asia and South Pacific Design Automation 2003
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Programs as a-Reference
308
3 12
Session 4A
Modeling for Floorplan
319
xxx
4A-2 Multi-level Placement for Large-scale Mixed-Size IC Designs
325
33 1
Session 4B
(338
342
Organizers ...
-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs Anurag Tiwari, Karen A. ...
doi:10.1109/aspdac.2003.1194983
fatcat:obdbe4dwivgsfpbeuvb7s73fpe
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow
2015
2015 25th International Conference on Field Programmable Logic and Applications (FPL)
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We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. ...
A second extension to VTR generates a configuration bitstream for the FPGA; that is, the bitstream configures the FPGA to realize a user-provided placed and routed design. ...
However, since it processes the whole design at once, it is too run-time and memory intensive to be a viable approach for a large design. ...
doi:10.1109/fpl.2015.7293955
dblp:conf/fpl/KimA15
fatcat:wrsq6lssqvbyvbu4gr7wbuuc6m
FPGA Dynamic and Partial Reconfiguration
2018
ACM Computing Surveys
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We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. ...
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). ...
CoPR first uses the vendor synthesis tool (XST) to synthesise all modules for the target FPGA to determine resource requirements. ...
doi:10.1145/3193827
fatcat:tbks3e734zdkdceihncpdeawia
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