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Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
2008 2008 Asia and South Pacific Design Automation Conference  
And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch.  ...  The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced  ...  And their effect on the circuit performance can be largely eliminated by layout techniques such as symmetry constraint.  ... 
doi:10.1109/aspdac.2008.4484055 dblp:conf/aspdac/LiuDHWHG08 fatcat:atqp4ypks5asjd5tyyg5x2nmgu

A CMOS analog circuit for Gaussian functions

J. Madrenas, M. Verleysen, P. Thissen, J.L. Voz
1996 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
Flandre for fruitful discussions on transistor characterization and fabrication.  ...  Design constraints and mismatch effects are discussed, as well as the layout optimization. The circuit-has been designed in a SOI technology and manufactured.  ...  LIMITATIONS OF MISMATCH Since the circuit is based on the symmetry of a current mirror, performance is limited by mismatches in the Mi -Ma and Ma -M4 pairs.  ... 
doi:10.1109/82.481479 fatcat:ytkhkfkkxzepvl6qrwamctdjee

A roadmap and vision for physical design

Andrew B. Kahng
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
technology.  ...  . (5) The scope of physical design must expand (up to package and system, down to manufacturing interfaces, out to novel implementation technologies, etc.), even as renewed focus is placed on basic optimization  ...  ., by hybrid analog-digital compensation for device mismatch. Isolation techniques must be flexibly applied.  ... 
doi:10.1145/505388.505416 dblp:conf/ispd/Kahng02 fatcat:6xefj4rzmbhkrab7uskhi6s2ya

A roadmap and vision for physical design

Andrew B. Kahng
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
technology.  ...  . (5) The scope of physical design must expand (up to package and system, down to manufacturing interfaces, out to novel implementation technologies, etc.), even as renewed focus is placed on basic optimization  ...  ., by hybrid analog-digital compensation for device mismatch. Isolation techniques must be flexibly applied.  ... 
doi:10.1145/505415.505416 fatcat:qphnbldeyzcpbhl2bpqyuzdwsa

TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability

Keunwoo Kim, Jente B. Kuang, Fadi H. Gebara, Hung C. Ngo, Ching-Te Chuang, Kevin J. Nowka
2009 IEEE Transactions on Electron Devices  
The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies.  ...  This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies.  ...  Since V T matching is important for sense amplifiers, common centroid layout style and symmetry (i.e., analog style layout) [12] are required for best circuit performance for both front and back gates  ... 
doi:10.1109/ted.2009.2030657 fatcat:4j64xbge35c3dkd2yztqfv3w3i

High-performance CMOS variability in the 65-nm regime and beyond

K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, N. J. Rohrer
2006 IBM Journal of Research and Development  
The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth.  ...  In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed.  ...  . ** Trademark, service mark, or registered trademark of Nintendo in the United States, other countries, or both.  ... 
doi:10.1147/rd.504.0433 fatcat:ij2vpwacyzfvbfjumtpatz63wm

High Performance CMOS Variability in the 65nm Regime and Beyond

Sani Nassif, Kerry Bernstein, David J. Frank, Anne Gattiker, Wilfried Haensch, Brian L. Ji, Ed Nowak, Dale Pearson, Norman J. Rohrer
2007 2007 IEEE International Electron Devices Meeting  
The manner in which tolerance is specified and accommodated in high-performance design changes dramatically as CMOS technologies scale beyond a 90-nm minimum lithographic linewidth.  ...  In this paper, predominant contributors to variability in new CMOS devices are surveyed, and preferred approaches to mitigate their sources of variability are proposed.  ...  By adhering to these strict layout rules for environmental symmetry, systematic variations are mostly removed so that the analog circuit is subject predominantly to local mismatch due to random variations  ... 
doi:10.1109/iedm.2007.4419002 fatcat:hfmoqtlzkfgajjmwqcsltnwg4u

A Process Variation Tolerant Self-Compensating Sense Amplifier Design

Aarti Choudhary, Sandip Kundu
2009 2009 IEEE Computer Society Annual Symposium on VLSI  
the conventional bulk type CMOS based sense amplifier on 32nm technology node.  ...  SOI based device structures incorporated by AMD, Honeywell, IBM has resulted in exponential growth of performance and integration density of silicon CMOS technology.  ... 
doi:10.1109/isvlsi.2009.50 dblp:conf/isvlsi/ChoudharyK09 fatcat:7d4ncb2rpbdxnmjhziormvjine

Performance of Quad Mass Gyroscope in the Angular Rate Mode

Sina Askari, Mohammad H. Asadian, Andrei M. Shkel
2021 Micromachines  
For each method of instrumentation, we presented constraints on selection of control parameters with respect to the Q-factor of the devices.  ...  In this paper, the characterization and analysis of a silicon micromachined Quad Mass Gyroscope (QMG) in the rate mode of operation are presented.  ...  Simon which resulted in several patents on the topic. Methodology for  ... 
doi:10.3390/mi12030266 pmid:33806651 fatcat:ah6gwzoa7vbgdnxbtx4foywgmy

Foucault pendulum on a chip: Rate integrating silicon MEMS gyroscope

Igor P. Prikhodko, Sergei A. Zotov, Alexander A. Trusov, Andrei M. Shkel
2012 Sensors and Actuators A-Physical  
Due to the stiffness and damping symmetry, and low energy dissipation, the gyroscope can be instrumented for direct angle measurements with fundamentally unlimited rotation range and bandwidth.  ...  both bandwidth and range constraints of conventional open-loop Coriolis vibratory rate gyroscopes.  ...  Heer from Zurich Instruments for assistance with interface electronics, B. Simon for aid in finite element modeling, Dr. D. Lynch and Prof. R. M'Closkey for expert suggestions.  ... 
doi:10.1016/j.sna.2012.01.029 fatcat:wjowg2fwyncd3obxwncsym2lky

High-Range Angular Rate Sensor Based on Mechanical Frequency Modulation

Sergei A. Zotov, Alexander A. Trusov, Andrei M. Shkel
2012 Journal of microelectromechanical systems  
We report, for the first time, an angular rate sensor based on mechanical frequency modulation (FM) of the input rotation rate.  ...  Structural characterization of a vacuumpackaged QMG showed Q factors on the order of one million over a wide temperature range from −40 • C to +100 • C with a relative x/y mismatch of Q of 1%.  ...  Prikhodko for the assistance with the experimental characterization of the prototype and I. Chepurko for the assistance with the interface electronics.  ... 
doi:10.1109/jmems.2011.2178116 fatcat:fz5b7puhmjfqda3sccaetdim2e

Grating-Assisted Fiber to Chip Coupling for SOI Photonic Circuits

Siddharth Nambiar, Purnima Sethi, Shankar Selvaraja
2018 Applied Sciences  
In the past decade, considerable effort has been made for designing efficient grating couplers on Silicon-on-Insulator (SOI) and other allied photonic platforms.  ...  In this article, we review the recent advances made to develop grating coupler designs for a variety of applications on SOI platform.  ...  SOI chip placed in the base.  ... 
doi:10.3390/app8071142 fatcat:rr4yy7cdy5agnkw6pivwvyyq54

Hyperuniform disordered waveguides and devices for near infrared silicon photonics

Milan M. Milošević, Weining Man, Geev Nahal, Paul J. Steinhardt, Salvatore Torquato, Paul M. Chaikin, Timothy Amoah, Bowen Yu, Ruth Ann Mullen, Marian Florescu
2019 Scientific Reports  
We introduce a hyperuniform-disordered platform for the realization of near-infrared photonic devices on a silicon-on-insulator platform, demonstrating the functionality of these structures in a flexible  ...  An integrated design for a compact, sub-volt, sub-fJ/bit, hyperuniform-clad, electrically controlled resonant optical modulator suitable for fabrication in the silicon photonics ecosystem is presented  ...  of six-fold symmetry in two dimensions).  ... 
doi:10.1038/s41598-019-56692-5 pmid:31889165 pmcid:PMC6937303 fatcat:2yy2ttpwyjhd5gaux5ssnjzi5i

CORNERSTONE's Silicon Photonics Rapid Prototyping Platforms: Current Status and Future Outlook

Callum G. Littlejohns, David J. Rowe, Han Du, Ke Li, Weiwei Zhang, Wei Cao, Thalia Dominguez Bucio, Xingzhao Yan, Mehdi Banakar, Dehn Tran, Shenghao Liu, Fanfan Meng (+21 others)
2020 Applied Sciences  
of production volumes, whilst also retaining the ability for device level innovation, crucial for researchers, by offering flexibility in its process flows.  ...  The CORNERSTONE rapid-prototyping capability bridges this gap between research and industry by providing a rapid prototyping fabrication line based on deep-UV lithography to enable seamless scaling up  ...  The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.  ... 
doi:10.3390/app10228201 fatcat:txzk7q7k6vcojbt5l4l2tyyclm

SiGe Radio Frequency ICs for Low-Power Portable Communication

J.R. Long
2005 Proceedings of the IEEE  
The range and impact of SiGe bipolar and BiCMOS technologies on wireless transceivers for portable telephony and data communications are surveyed.  ...  The performance of on-chip passive components in silicon technologies are also reviewed in this paper.  ...  (even in SOI technology, where devices and the insulating layer are bonded to or fabricated on a semiconducting substrate).  ... 
doi:10.1109/jproc.2005.852227 fatcat:fszoseeh4jc2bgy35ggcdnxkju
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