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Symmetric Arithmetic Circuits [article]

Anuj Dawar, Gregory Wilsenach
2021 arXiv   pre-print
We introduce symmetric arithmetic circuits, i.e. arithmetic circuits with a natural symmetry restriction.  ...  We establish unconditional exponential lower bounds on the size of any symmetric circuit for computing the permanent.  ...  Though symmetric arithmetic circuits have not previously been studied, symmetric Boolean circuits have [15, 23, 2, 24] .  ... 
arXiv:2002.06451v2 fatcat:unqswydznrdilitkbpza5gfsdu

Symmetric Arithmetic Circuits

Anuj Dawar, Gregory Wilsenach, Emanuela Merelli, Anuj Dawar, Artur Czumaj
2020 International Colloquium on Automata, Languages and Programming  
We introduce symmetric arithmetic circuits, i.e. arithmetic circuits with a natural symmetry restriction.  ...  In contrast, we show that there are polynomial-size symmetric circuits for computing the determinant over fields of characteristic zero.  ...  Though symmetric arithmetic circuits have not previously been studied, symmetric Boolean circuits have [13, 20, 2] .  ... 
doi:10.4230/lipics.icalp.2020.36 dblp:conf/icalp/DawarW20 fatcat:hjjh3sbiwbcuzdakr2cak5v44m

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon
2013 Journal of Electrical and Computer Engineering  
We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs.  ...  Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to  ...  The goal of this paper is to develop circuit topologies and configurations that lead to high-performance low leakage arithmetic components using symmetric four-terminal FinFETs.  ... 
doi:10.1155/2013/454392 fatcat:umbmxbytuzautjlhg5mirxxwbu

Symmetric Arithmetic Circuits [article]

Anuj Dawar, Gregory Wilsenach, Apollo-University Of Cambridge Repository, A Czumaj, A Dawar, E Merelli
2020
We introduce symmetric arithmetic circuits, i.e. arithmetic circuits with a natural symmetry restriction.  ...  In contrast, we show that there are polynomial-size symmetric circuits for computing the determinant over fields of characteristic zero.  ...  Though symmetric arithmetic circuits have not previously been studied, symmetric Boolean circuits have [14, 21, 2] .  ... 
doi:10.17863/cam.56098 fatcat:zlpxdqyccbgnvgqws7gmo77lsi

On the Complexity of Symmetric Polynomials

Markus Bläser, Gorav Jindal, Michael Wagner
2018 Innovations in Theoretical Computer Science  
Furthermore, we study the complexity of testing whether a function is symmetric. For polynomials, this question is equivalent to arithmetic circuit identity testing.  ...  As a corollary of this result, we show that if VP = VNP then there exist symmetric polynomial families which have super-polynomial arithmetic complexity.  ...  Given an arithmetic circuit C computing the polynomial f (x 1 , x 2 , . . . , x n ), check if f is a symmetric polynomial?  ... 
doi:10.4230/lipics.itcs.2019.47 dblp:conf/innovations/BlaserJ19 fatcat:lq7xln6rwvcvnby7ggqxzinlry

Arithmetic optimization for custom instruction set synthesis

Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
2009 2009 IEEE 7th Symposium on Application Specific Processors  
Unlike earlier work (e.g., Three Greedy Approach [1], [2]) our approach does not require any prior knowledge about the functionality of the circuit.  ...  The proposed technique automatically infers the use of carry-save arithmetic, when appropriate, and suppresses its use when unfavorable.  ...  Logic synthesis techniques work quite well for finite state machines and control dominated circuits, but are generally ineffective for arithmetic circuits, meaning that there is a large gap between arithmetic  ... 
doi:10.1109/sasp.2009.5226336 dblp:conf/sasp/VermaZBI09 fatcat:zfwct4kis5e6jcrisn47net3gi

Affine projections of symmetric polynomials

Amir Shpilka
2002 Journal of computer and system sciences (Print)  
We refer to this model as the symmetric model. This new model is related to standard models of arithmetic circuits, especially to depth-3 circuits.  ...  In this paper, we introduce a new model for computing polynomials-a depth-2 circuit with a symmetric gate at the top and plus gates at the bottom, i.e. the circuit computes a symmetric function in linear  ...  Definition 2. 2 . 2 A depth-2 symmetric arithmetic circuit is a layered graph with two levels.  ... 
doi:10.1016/s0022-0000(02)00021-1 fatcat:mm7gujcfbja23mddrnk3z4gu5e

Data-Width-Driven Power Gating of Integer Arithmetic Circuits

Tung Thanh Hoang, Per Larsson-Edefors
2012 2012 IEEE Computer Society Annual Symposium on VLSI  
We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data.  ...  When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power.  ...  First we consider the arithmetic circuit netlist as a graph.  ... 
doi:10.1109/isvlsi.2012.59 dblp:conf/isvlsi/HoangL12 fatcat:euujngraznbfzhn6lyqq6sc3a4

Symmetric Determinantal Representation of Weakly-Skew Circuits

Bruno Grenet, Erich L. Kaltofen, Pascal Koiran, Natacha Portier, Marc Herbstritt
2011 Symposium on Theoretical Aspects of Computer Science  
We deploy algebraic complexity theoretic techniques for constructing symmetric determinantal representations of weakly-skew circuits, which include formulas.  ...  formula or a weakly-skew circuit).  ...  We thank Meena Mahajan for pointing out [13] and sketching the construction of a symmetric determinant of size O(n 3 ) from a determinant of size n.  ... 
doi:10.4230/lipics.stacs.2011.543 dblp:conf/stacs/GrenetKKP11 fatcat:lkeemh3dnbcjloosj7nigiongu

Page 1118 of Mathematical Reviews Vol. , Issue 87b [page]

1987 Mathematical Reviews  
This paper presents a theoretical approach to a new class of nonbinary arithmetic AN codes using symmetric R-ary expres- sions and Lee-type arithmetic distance.  ...  “Following the introductory descriptions of symmetric R-ary expressions, some important properties of the arithmetic distance and the error correctabilities of the codes are discussed.  ... 

Lower bounds on arithmetic circuits via partial derivatives

Noam Nisan, Avi Wigderson
1996 Computational Complexity  
In this paper we describe a new technique for obtaining lower bounds on restriced classes of nonmonotone arithmetic circuits.  ...  We use the technique to obtain new lower bounds for computing symmetric polynomials and iterated matrix prod-  ...  This sad state of affairs is essentially also true for arithmetic circuits, a natural model for computing arithmetic functions (see e.g. [9] ).  ... 
doi:10.1007/bf01294256 fatcat:ro7foiksize4lb33vidkglz6oy

Smaller ACC0 Circuits for Symmetric Functions [article]

Brynmor Chapman, Ryan Williams
2021 arXiv   pre-print
That is, depth-3 CC^0 circuits can compute any symmetric function in subexponential size.  ...  We construct MOD_m circuits computing symmetric functions with non-prime power m, with size-depth tradeoffs that beat the longstanding lower bounds for AC^0[m] circuits for prime power m.  ...  In order to apply the elementary symmetric polynomials, our construction also involves arithmetic circuits over prime fields.  ... 
arXiv:2107.04706v1 fatcat:qc6zzlxpovfyxhkndnvo2ng3uy

Page 652 of Mathematical Reviews Vol. , Issue 88b [page]

1988 Mathematical Reviews  
N>0O such that every d-p(n) symmetric circuit with n > N inputs has its corresponding subset including or  ...  A function n+ K(n) C {0,1,..., n} is circuit-definable if there exists a sequence C,, of d-p(n) symmetric circuits of n inputs (n € N) for some fixed polynomial p and a constant d, such that the cor- responding  ... 

Faster Bootstrapping of FHE over the integers with large prime message space [article]

Zhizhu Lian, Yupu Hu, Hu Chen, Baocang Wang
2019 IACR Cryptology ePrint Archive  
In this paper, we express this double modulo reduction circuit as a arithmetic circuit of degree at most θ 2 log 2 θ/2, with O(θ log 2 θ) multiplication gates, where θ = λ log λ and λ is the security parameter  ...  Bootstrapping of FHE over the integer with large message is a open problem, which is to evaluate double modulo (c mod p) mod Q arithmetic homomorphically for large Q.  ...  The following lemma 1 states Ben-or's observation that multilinear symmetric polynomials can be computed by restricted depth-3 arithmetic circuits that perform interpolation.  ... 
dblp:journals/iacr/LianHCW19 fatcat:o5avzofofngjfmjrqplz6metjm

Page 2098 of Mathematical Reviews Vol. , Issue 80E [page]

1980 Mathematical Reviews  
Information and communication, circuits Author’s summary: “An arithmetic-logical device is described which secures effective execution of arithmetic and logical opera- tions, over fields of bits of arbitrary  ...  Authors’ summary: “We show that it is possible to shorten calcu- lations in the structural synthesis of RLC-circuits whose conduc- tivity graphs are symmetric.  ... 
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