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Formal verification of digital circuits using symbolic ternary system models [chapter]

R. Bryant, C.-J. Seger
1991 Computer-Aided Verification '90  
An assertion is verified by translating it into a sequence of patterns and checks for a ternary symbolic simulator. This methodology has been used to verify a number of full scale circuit designs.  ...  This paper presents a formal methodology for verifying synchronous digital circuits using a ternary system model.  ...  A step-level symbolic trajectory formula is defined recursively as: 1. Constants: TRUE is a trajectory formula.  ... 
doi:10.1090/dimacs/003/11 dblp:conf/dimacs/BryantS90 fatcat:gsvkorkv75as7grx2z7wqqudpi

An industrially effective environment for formal hardware verification

C.-J.H. Seger, R.B. Jones, J.W. O'Leary, T. Melham, M.D. Aagaard, C. Barrett, D. Syme
2005 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight  ...  The Forte formal verification environment for datapath-dominated hardware is described.  ...  The authors are particularly grateful to the users of Forte at Intel and to the Intel design teams who supplied case studies for their own example verifications.  ... 
doi:10.1109/tcad.2005.850814 fatcat:rxashd5osrhcjky5mgq2jsodk4

Some Thoughts on Runtime Verification [chapter]

Oded Maler
2016 Lecture Notes in Computer Science  
Some reflections on verification and runtime verification in general and of cyber-physical systems in particular.  ...  I start in Section 2 with a reflection on the nature of words and then discuss some potential meanings of runtime verification as distinct from just verification.  ...  Section 4 discusses runtime verification interpreted as verification of something closer to the implementation.  ... 
doi:10.1007/978-3-319-46982-9_1 fatcat:nms5ig442bhrjn22z742rg7suy

A compositional circuit model and verification by composition [chapter]

Zheng Zhu
1995 Lecture Notes in Computer Science  
Symbolic Trajectory Evaluation (STE) is a theory for digital circuit verification.  ...  In the last a few years, STE has been used in proving practical digital circuits and has been proven a practical methodology with a mathematical foundation in circuit verification.  ...  Domain of Discourse In symbolic trajectory evaluation, a circuit is modeled as operating over logic levels O, 1, a third value 3_ representing an indeterminate or unknown level, and a fourth value T, representing  ... 
doi:10.1007/3-540-59047-1_44 fatcat:7l2e7mjkkfga5nyiglma3j6xsm

A Survey of Hybrid Techniques for Functional Verification

Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
2007 IEEE Design & Test of Computers  
Acknowledgments Sandip Ray is partially supported by DARPA and the National Science Foundation under grant CNS-0429591.  ...  Trajectory evaluation and theorem proving Joyce and Seger experimented with combining trajectory evaluation with theorem proving.  ...  They used symbolic trajectory evaluation (STE) to prove a circuit's low-level properties, and combined these properties to prove the toplevel specification through a mechanical theorem prover.  ... 
doi:10.1109/mdt.2007.30 fatcat:ojmxdheqenekzor2ybvtf7z3hi

Formal verification of PowerPC arrays using symbolic trajectory evaluation

Manish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
The formal method of symbolic trajectory evaluation (STE) appears to offer a solution, however. STE verifies that a circuit satisfies a formula in a carefully restricted temporal logic.  ...  The circuit is modeled at the switch level, so the verification is done on the actual design.  ...  Bryant and Seger developed the theory of Symbolic Trajectory Evaluation towards that end [10] . In STE, properties of circuits are expressed in a restricted temporal logic.  ... 
doi:10.1145/240518.240641 dblp:conf/dac/PandeyRBB96 fatcat:tg4gvtazbndzphv2fkquxa3rr4

A Scalable Symbolic Simulator for Verilog RTL

Sasidhar Sunkari, Supratik Chakraborty, Vivekananda Vedula, Kailasnath Maneparambil
2007 2007 Eighth International Workshop on Microprocessor Test and Verification  
Symbolic simulation is an important technique used in formal property verification and test generation for digital circuits.  ...  In this paper, we present some exploratory ideas for performing word-level symbolic simulation over a Verilog RTL description of a circuit.  ...  Acknowledgment The authors would like to thank Ashutosh Kulkarni and Kaustubh Nimkar for their inputs and help in the implementation of the symbolic simulator.  ... 
doi:10.1109/mtv.2007.13 dblp:conf/mtv/SunkariCVM07 fatcat:j4dgegytybazlghcj56yp6omkq

Integration Verification in System on Chips Using Formal Techniques [chapter]

Subir K
2009 Micro Electronic and Mechanical Systems  
Generalized symbolic trajectory evaluations Symbolic trajectory evaluation (STE) provides a means to formally verify properties of a sequential system by a modified form of symbolic simulation.  ...  In [6] the combining of theorem proving and trajectory evaluation is explored, with a motivation to gain the benefits of both the approaches.  ... 
doi:10.5772/7022 fatcat:2h5w33bigndidgyu6zm5e7b5oq

Formal Verification of Hybrid Automotive Systems [chapter]

Jairam Sukumar, Subir K, Kusum Lata, Navakanta Bhat
2010 Motion Control  
SSF based methods are the most widely used platforms across the industry for hybrid and real time system.  ...  We introduce Simulink-Stateflow based modelling and verification platform [1], as shown in Figure 1 .  ...  Public domain quantifier elimination tools such as REDLOG ( [22] ) and QEPCAD ( [23] ) implement these approaches and have been used in symbolic verification of hybrid systems.  ... 
doi:10.5772/6963 fatcat:nmpq67qw6rbixoeoefx6xuo2ta

Formal Verification of Explicitly Parallel Microprocessors [chapter]

Byron Cook, John Launchbury, John Matthews, Dick Kieburtz
1999 Lecture Notes in Computer Science  
Acknowledgments For their contributions to this research, we thank Mark Aagaard Acknowledgements We wish to thank Byron Cook, Sava Krstic, and John Launchbury for their valuable contributions to this  ...  The author is supported by a graduate research fellowship with the National Science Foundation, and grants from the Air Force Material Command (F19628-93-C-0069) and Intel Strategic CAD Labs.  ...  ,AND SEGER, C.-J. H. Symbolic trajectory evaluation. In Formal Hardware Verification. Springer-Verlog, 1997. JONES, M. P. Qualified Types: Theory and Practice.  ... 
doi:10.1007/3-540-48153-2_4 fatcat:pd5w6ggq6fdpxfeqwiprqxintu

Experiences in Applying Formal Verification in Robotics [chapter]

Dennis Walter, Holger Täubig, Christoph Lüth
2010 Lecture Notes in Computer Science  
In this paper we report on our experiences with one such effort, which was concerned with designing, implementing and certifying a safety function for autonomous vehicles and robots.  ...  These pertain to the development process, the abstraction level at which specifications should be formulated, and the interplay between simulation and verification, among others.  ...  First and foremost, we assume the robots braking trajectory to be a straight line or a circular arc; in other words, the steering of the vehicle remains fixed until the vehicle has completely stopped.  ... 
doi:10.1007/978-3-642-15651-9_26 fatcat:6z5sorcyfba65auf2dttrkm3jm

Formal verification of analog and mixed signal designs: A survey

Mohamed H. Zaki, Sofiène Tahar, Guy Bois
2008 Microelectronics Journal  
Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation.  ...  In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior.  ...  BDD based symbolic algorithms and satisfiability modulo theories (SMT) [37] techniques are then applied in [38, 39] to check for properties of the design.  ... 
doi:10.1016/j.mejo.2008.05.013 fatcat:527gyri32nd3vjmnfavyiud36m

Automated Conformance Verification of Hybrid Systems

Harald Brandl, Martin Weiglhofer, Bernhard K. Aichernig
2010 2010 10th International Conference on Quality Software  
Due to the combination of discrete events and continuous behavior the validation of hybrid systems is a challenging task.  ...  Nevertheless, as for other systems the correctness of such hybrid systems is a major concern. In this paper we present a new approach for verifying the input-output conformance of two hybrid systems.  ...  The contribution of this work is threefold: (1) definition of an LTS semantics for hybrid systems by the introduction of qual events, (2) implementation of a tool for conformance verification, and (3)  ... 
doi:10.1109/qsic.2010.53 dblp:conf/qsic/BrandlWA10 fatcat:5hdim6ndyffkvlculpgywaa6c4

Automating the Verification of Floating-Point Programs [chapter]

Clément Fumex, Claude Marché, Yannick Moy
2017 Lecture Notes in Computer Science  
Our approach is implemented in the Why3 environment and its front-end SPARK 2014 for the development of safety-critical Ada programs.  ...  The level of proof success and proof automation highly depends on the way the floating-point operations are interpreted in the logic supported by back-end provers.  ...  Conclusions and Perspectives Our approach for automated verification of floating-point programs relies on a generic theory, written in Why3's specification language, to model FP arithmetic.  ... 
doi:10.1007/978-3-319-72308-2_7 fatcat:pj5a5gredzeu7ezxshgnrrjowe

Safety Verification of Neural Network Controlled Systems [article]

Arthur Clavière, Eric Asselin, Christophe Garion
2020 arXiv   pre-print
We assume a generic model for the controller that can capture both simple and complex behaviours involving neural networks.  ...  In this paper, we propose a system-level approach for verifying the safety of neural network controlled systems, combining a continuous-time physical system with a discrete-time neural network based controller  ...  In other words, the bottom element symbolically represents the "terminated" state of C.  ... 
arXiv:2011.05174v1 fatcat:3spgdx5sszedtjvwxokuqiyime
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