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Analyzing Fair Parametric Extended Automata [chapter]

Ahmed Bouajjani, Aurore Collomb-Annichini, Yassine Lakhnech, Mihaela Sighireanu
2001 Lecture Notes in Computer Science  
We address the problem of verifying safety and liveness properties for in nite-state systems, using symbolic reachability analysis.  ...  The models we consider are fair parametric extended automata, i.e., counter automata with parametric guards, supplied with fairness conditions on their transitions.  ...  It is a system with two clocks c 1 and c 2 and a counter x (see Figure 3 sender and c 2 the clock of a receiver.  ... 
doi:10.1007/3-540-47764-0_19 fatcat:fpujrtbburduvlrfxvsfj2jwr4

Language Preservation Problems in Parametric Timed Automata [article]

Étienne André, Didier Lime, Nicolas Markey
2020 arXiv   pre-print
Parametric timed automata (PTA) are a powerful formalism to model and reason about concurrent systems with some unknown timing delays.  ...  On the other hand, we exhibit decidable subclasses: 1-clock PTA, and 1-parameter deterministic L-PTA and U-PTA.  ...  Despite this flexibility, TA enjoy efficient algorithms for checking reachability (and many other properties), which makes them a well-suited model for reasoning about real-time systems.  ... 
arXiv:1807.07091v3 fatcat:fqr73bshojgpzag6n6hedw4t4m

Language Preservation Problems in Parametric Timed Automata

Étienne André, Didier Lime, Nicolas Markey
2018 Logical Methods in Computer Science  
Parametric timed automata (PTA) are a powerful formalism to model and reason about concurrent systems with some unknown timing delays.  ...  On the other hand, we exhibit decidable subclasses: 1-clock PTA, and 1-parameter deterministic L-PTA and U-PTA.  ...  Despite this flexibility, TA enjoy efficient algorithms for checking reachability (and many other properties), which makes them a well-suited model for reasoning about real-time systems.  ... 
doi:10.23638/lmcs-16(1:5)2020 fatcat:f6tfmuutb5edrm2tdup7umo3dm

Parametric real-time reasoning

Rajeev Alur, Thomas A. Henzinger, Moshe Y. Vardi
1993 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing - STOC '93  
We address the more realistic and more ambitious problem of deriving symbolic constraints on the timing properties required of real-time systems (e.g., \message delivery within the time it takes to execute  ...  There remains a gap between the automata classes for which w e know that emptiness is decidable and undecidable, respectively, and this gap is related to various hard and open problems of logic and automata  ...  In this paper, we attempt to lay the foundations for a theory of parametric reasoning about real time.  ... 
doi:10.1145/167088.167242 dblp:conf/stoc/AlurHV93 fatcat:dfo6ljqo5vdszh7j6fuwpdymqe

Reachability and liveness in parametric timed automata [article]

Étienne André, Didier Lime, Olivier H. Roux
2022 arXiv   pre-print
Parametric timed automata (PTAs) are a classical formalism for such systems but for which most interesting problems are undecidable.  ...  the system has a deadlock is however undecidable; (3) the problem of the existence of a valuation for which a run remains in a given set of locations exhibits a very thin border between decidability and  ...  Acknowledgments This work was partially supported by the ANR national research program "PACS" (ANR-14-CE28-0002) and by the ANR-NRF French-Singaporean research program ProMiS (ANR-19-CE25-0015).  ... 
arXiv:2004.09171v4 fatcat:lzldpbkrprexznc3z3nzavjlbq

Formal verification of timed systems: a survey and perspective

Farn Wang
2004 Proceedings of the IEEE  
We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and  ...  An overview of the current state of the art of formal verification of real-time systems is presented.  ...  [21] have extended DBM with parameters for the semialgorithmic analysis of counter and clock systems. B.  ... 
doi:10.1109/jproc.2004.831197 fatcat:7e5u5rvdbncqbmkku7szkdyz34

Consistency in Parametric Interval Probabilistic Timed Automata

Étienne André, Benoît Delahaye, Paulin Fournier
2019 Journal of Logical and Algebraic Methods in Programming  
We propose a new abstract formalism for probabilistic timed systems, Parametric Interval Probabilistic Timed Automata, based on an extension of Parametric Timed Automata and Interval Markov Chains.  ...  In the context of Interval Probabilistic Timed Automata (with no timing parameters), we show that this problem is decidable and propose a constructive algorithm for its resolution.  ...  Timed automata [1] are a widely recognized modeling formalism for reasoning about realtime systems.  ... 
doi:10.1016/j.jlamp.2019.04.007 fatcat:3injmbg2trc35djzurzucszste

What's Decidable About Parametric Timed Automata? [chapter]

Étienne André
2016 Communications in Computer and Information Science  
Parametric timed automata (PTA) are a powerful formalism to reason, simulate and formally verify critical real-time systems.  ...  We provide here a survey of decision and computation problems for PTA.  ...  Acknowledgements This manuscript benefited from discussions with Didier Lime, Nicolas Markey, and Olivier H. Roux.  ... 
doi:10.1007/978-3-319-29510-7_3 fatcat:l6iugmbrjjfnja2oz767fbufaa

Integer Parameter Synthesis for Real-Time Systems

Aleksandra Jovanovic, Didier Lime, Olivier H. Roux
2015 IEEE Transactions on Software Engineering  
We provide a subclass of parametric timed automata (PTA) that we can actually and efficiently analyze, and we argue that it retains most of the practical usefulness of PTA for the modeling of real-time  ...  systems.  ...  Acknowledgments The authors thank the anonymous reviewers for their very useful comments.  ... 
doi:10.1109/tse.2014.2357445 fatcat:n4zjv4cbyrdqla2bmsxzrkcg3y

A hybrid verification approach: Getting deep into the design

S. Hazelhurst, G. Kamhi, O. Weissberg, L. Fix
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
We propose a hybrid verification technology combining symbolic trajectory evaluation with either symbolic model checking or SATbased model checking.  ...  This reduces significantly the cost (both human and computing) of verifying circuits with complex initialisation, as well as simplifying proof development by enhancing verification productivity.  ...  When it terminates, we have the initial states for SMC. This is converted from the parametric to the characteristic representation (this conversion takes into about the s).  ... 
doi:10.1109/dac.2002.1012604 fatcat:nqropdlokrgupgl6qz73ilskdq

Verification of Infinite State Systems [chapter]

Ahmed Bouajjani
2003 Lecture Notes in Computer Science  
reasoning about families of systems, e.g., networks of processes, • process mobility, dynamic creation and destruction of processes (dynamic modification of the communication structure).  ...  Such problems rise naturally as soon as we consider aspects like: • real-time constraints: timed and hybrid systems, • unbounded discrete data structures: counters, fifo-channels, stacks, etc. • parametric  ...  Networks 22 26 Symbolic techniques for parametric reasoning 24 1 Regular Model Checking Bengt Jonsson Joint work with Marcus Nilsson, Parosh Abdulla, Ahmed Bouajjani, and Tayssir Touili.  ... 
doi:10.1007/978-3-540-45220-1_7 fatcat:4j5lzdbfc5hd7ptdo4tpwvmd2m

Fully automatic verification and error detection for parameterized iterative sequential circuits [chapter]

Tiziana Margaria
1996 Lecture Notes in Computer Science  
This allows us to apply the corresponding decision procedure and counter-model generator implemented in the Mona verification tool, which, for the first time, yields 'push-button' verification, and error  ...  detection and diagnosis for the considered class of circuits.  ...  Thanks are also due to David Basin and Nils Klarlund for earlier discussions, help in getting acquainted with Mona, and for their initial implementation of the counter and other examples in Mona.  ... 
doi:10.1007/3-540-61042-1_49 fatcat:rjimk4w3xjeutbsrkope2k6fdm

Robust synthesis for real-time systems

Kim G. Larsen, Axel Legay, Louis-Marie Traonouez, Andrzej Wąsowski
2014 Theoretical Computer Science  
Specification theories for real-time systems allow reasoning about interfaces and their implementation models, using a set of operators that includes satisfaction, refinement, logical and parallel composition  ...  Finally, we consider the parametric robustness problem and propose a counterexample refinement heuristic for computing safe perturbation values.  ...  We extend the work of [21, 22] by considering compositional design operators, stepwise-refinement, and reasoning about open systems (only closed system composition were considered so far).  ... 
doi:10.1016/j.tcs.2013.08.015 fatcat:2bslg2jmkzepbpl6uul7z6mcz4

On the expressive power of invariants in parametric timed automata [article]

Étienne André, Didier Lime, Mathias Ramparison
2019 arXiv   pre-print
Parametric timed formalisms, such as parametric timed automata (PTAs), tackle the synthesis of such timing constants (seen as parameters) for which a property holds.  ...  We believe our formalism allows for an interesting trade-off between decidability and practical expressiveness and is therefore promising. We show its applicability in a small case study.  ...  about PTAU I .  ... 
arXiv:1908.06633v1 fatcat:w76qccnq4bgbbh47hl2x47wu7i

A logic-based modeling and verification of CPS

Neda Saeedloei, Gopal Gupta
2011 ACM SIGBED Review  
Cyber-physical systems (CPS) consist of perpetually and concurrently executing physical and computational components.  ...  Interesting properties of the system can be verified merely by posing appropriate queries to this model. Precise parametric analysis can also be performed.  ...  Co-induction is a powerful technique for reasoning about unfounded sets, unbounded structures, and interactive computations. Elegant co-inductive extensions of logic programming have been proposed.  ... 
doi:10.1145/2000367.2000374 fatcat:uwpfdczyd5eg5jkkmsad5xjmru
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