Filters








9 Hits in 1.1 sec

Quality-of-service for a high-radix switch

Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor Mudge
2014 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)  
Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network sizes have increased, the complexity of these techniques has grown as well, particularly in the case of multi-hop
more » ... tworks. In this paper, we propose an efficient QoS implementation for a single-stage, high-radix switch, which is readily scalable to 64 nodes. In addition to best effort and guaranteed throughput services, we implement a guaranteed latency traffic class with a latency bound. Our implementation allows systems significantly larger than most current multi-core chips to be implemented without the need for difficult and complex multi-hop QoS.
doi:10.1109/dac.2014.6881490 fatcat:3a2mgc7fq5gapccbtgwiikxt3e

Quality-of-Service for a High-Radix Switch

Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor Mudge
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network sizes have increased, the complexity of these techniques has grown as well, particularly in the case of multi-hop
more » ... tworks. In this paper, we propose an efficient QoS implementation for a single-stage, high-radix switch, which is readily scalable to 64 nodes. In addition to best effort and guaranteed throughput services, we implement a guaranteed latency traffic class with a latency bound. Our implementation allows systems significantly larger than most current multi-core chips to be implemented without the need for difficult and complex multi-hop QoS.
doi:10.1145/2593069.2593194 dblp:conf/dac/AbeyratneJKBDDM14 fatcat:idgb5s2ykfgtfcnr7kgaplabxu

A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications

Xiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang, Inhee Lee, Dennis Sylvester, David Blaauw
2016 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)  
We present a discontinuous harvesting approach for switch capacitor DC-DC converters that enables ultra-low power energy harvesting. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst-mode, switching and leakage losses in the DC-DC converter can be optimally traded-off with the loss due to non-ideal MPPT operation. The harvester uses a 15pW mode controller, an automatic conversion ratio modulator, and a moving sum charge pump for low startup
more » ... upon a mode switch. In 180nm CMOS, the harvester achieves >40% end-to-end efficiency from 113pW to 1.5μW with 66pW minimum input power, marking a >10× improvement over prior ultra-low power harvesters.
doi:10.1109/vlsic.2016.7573490 pmid:28392977 pmcid:PMC5381925 dblp:conf/vlsic/WuSJYLSB16 fatcat:rxcwrfidyjempgaxti35exy75e

Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration

Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor Mudge, David Blaauw
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
This paper proposes a novel 3D switch, called 'Hi-Rise', that employs high-radix switches to efficiently route data across multiple stacked layers of dies. The proposed interconnect is hierarchical and composed of two switches per silicon layer and a set of dedicated layer to layer channels. However, a hierarchical 3D switch can lead to unfair arbitration across different layers. To address this, the paper proposes a unique class-based arbitration scheme that is fully integrated into the
more » ... ng fabric, and is easy to implement. It makes the 3D hierarchical switch's fairness comparable to that of a flat 2D switch with least recently granted arbitration. The 3D switch is evaluated for different radices, number of stacked layers, and different 3D integration technologies. A 64-radix, 128-bit width, 4-layer Hi-Rise evaluated in a 32nm technology has a throughput of 10.65 Tbps for uniform random traffic. Compared to a 2D design this corresponds to a 15% improvement in throughput, a 33% area reduction, a 20% latency reduction, and a 38% energy per transaction reduction.
doi:10.1109/micro.2014.45 dblp:conf/micro/JelokaDDMB14 fatcat:4asts2ifzff2tfpmrpk2dqlaam

Acknowledgment to Reviewers of Journal of Low Power Electronics and Applications in 2020

Journal of Low Power Electronics and Applications Editorial Office Journal of Low Power Electronics and Applications Editorial Office
2021 Journal of Low Power Electronics and Applications  
, Supreet Curiac, Daniel-Ioan Jendernalik, Waldemar De Sousa, Jose T.  ...  Paul Haubelt, Christian Bogdan, Razvan HEBRARD, Luc Cagli, Carlo Hoeppner, Sebastian Cai, Hao Hui, Teo Tee Chakraborty, Koushik Hwang, Yin-Tsung Chang, Yao-Feng Igual, Jorge Ciofi, Carmine Jeloka  ... 
doi:10.3390/jlpea11010008 fatcat:mt7xlt7zdbchxihogukguidfeq

Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems

Anand Savanth, Alex S. Weddell, James Myers, David Flynn, Bashir M. Al-Hashimi
2017 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
ACKNOWLEDGMENT The authors would like to thank ARM colleagues Pranay Prabhat, David Bull and Supreet Jeloka for useful discussions and reviews, and Dr.  ... 
doi:10.1109/tcsi.2017.2707304 fatcat:6a4xeovevbcxjpz3z5jtdwttfe

E-ECC

Hsing-Min Chen, Akhil Arunkumar, Carole-Jean Wu, Trevor Mudge, Chaitali Chakrabarti
2015 Proceedings of the 2015 International Symposium on Memory Systems - MEMSYS '15  
ACKNOWLEDGMENTS We would like to thank Supreet Jeloka for help with synthesis. This work was supported in part by the DARPA-PERFECT program.  ... 
doi:10.1145/2818950.2818961 dblp:conf/memsys/ChenAWMC15 fatcat:lr6doux5q5bdbhumk23jebmyoe

A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications

C. Samori, S. Levantino, V. Boccuzzi
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)  
Senior Fellow and Vice President, Micron Technology Inc.) 10am Session 22: Circuits for Machine Learning and cryo-CMOS Applications Chaired by: Visvesh Sathe (United States) and Supreet Jeloka (  ... 
doi:10.1109/cicc.2001.929755 fatcat:mfc6mywe2zgydbzpvnmw7bumqu

Efficient in-hardware compression of on-chip data

Amin Ghasemazar
2021
In SPDS, 2001. [18] Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, and Reetuparna Das. Compute caches.  ... 
doi:10.14288/1.0404515 fatcat:nxtj5xz4yffm7inyjyp7k6caem