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Mapping into LUT structures
2012
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Mapping into K-input lookup tables (K-LUTs) is an important step in synthesis for Field-Programmable Gate Arrays (FPGAs). ...
This paper proposes a modified FPGA architecture which allows for direct (non-routable) connections between adjacent LUTs. As a result, delay can be reduced but area may increase. ...
Acknowledgements This work has been supported in part by contacts from SRC (1875.001), NSA, and industrial sponsors: Actel, Altera, Atrenta, Cadence, Calypto, IBM, Intel, Jasper, Magma, Oasys, Real Intent ...
doi:10.1109/date.2012.6176724
dblp:conf/date/RayMEBJC12
fatcat:2a7ltrsgn5fzpo72wxcaqq23la
BDD-based logic synthesis for LUT-based FPGAs
2002
ACM Transactions on Design Automation of Electronic Systems
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This system performs network transformation, decomposition and optimization at an early stage to generate a network which can be directly mapped onto FPGAs. ...
With this system, both AND-OR decompositions and AND-XOR decompositions can be identified, resulting in large area savings for synthesized XOR-intensive circuits. ...
Maciej Ciesielski (Univ of Massachusetts, Amherst) and Congguang Yang (Chameleon Systems) for providing their logic synthesis tool, BDS, for use in our work. ...
doi:10.1145/605440.605442
fatcat:j6vwy7weynfyhairj24cmq3xxq
Teraflop FPGA Design
2011
2011 IEEE 20th Symposium on Computer Arithmetic
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User requirements for signal processing have increased in line with, or greater than, the increase in FPGA resources and capability. ...
devices have been traditionally architected for. ...
DEVICE CAPABILITY In recent FPGA architectures there has been some support of the multiplier sizes suited for floating point, although traditionally FPGA base multiplier sizes are at smaller fixed point ...
doi:10.1109/arith.2011.32
dblp:conf/arith/Langhammer10
fatcat:tg6iwj6a65chvgrshoaydzgpnq
Power-aware FPGA logic synthesis using binary decision diagrams
2007
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays - FPGA '07
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If technology mapping is tuned to achieve the same average delay for both SIS and BDD-based flows, a 3% average energy reduction is achieved by our new synthesis approach. ...
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. ...
We thank Julien Lamoureux from the University of British Columbia for providing the EMap software. We acknowledge the efforts of Mohammed Alhussein in preparing the final version of the paper. ...
doi:10.1145/1216919.1216945
dblp:conf/fpga/TinmaungHT07
fatcat:j6pavdhbfze7nadakn3bvuxnuu
Hybrid CMOS-STTRAM non-volatile FPGA: Design challenges and optimization approaches
2008
2008 IEEE/ACM International Conference on Computer-Aided Design
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In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework; identify the key design challenges; and propose optimization techniques at circuit, architecture and application mapping levels. ...
Simulation results show that a STTRAM based optimized FPGA framework achieves an average improvement of 48.38% in area, 22.28% in delay and 16.1% in dynamic power for ISCAS benchmark circuits over a conventional ...
Here we present an architecture for Shannon decomposition based dynamic supply gating for reducing static power components in the proposed framework. 1) Hardware support for Shannon decomposition: The ...
doi:10.1109/iccad.2008.4681636
dblp:conf/iccad/PaulMB08
fatcat:hzrpc2rfrvgcxlsim66x6aftb4
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks
2014
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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A complete mapping methodology including functional decomposition, fusion, and optimal packing of operations is proposed and efficiently used to reduce the large energy overhead of PIs. ...
This paper presents an energy-efficient heterogenous application mapping framework in FPGA, where the conventional application mappings to logic and DSP blocks (for DSP-enhanced FPGA devices) are combined ...
The decomposition allows storing a total of 2 α + 2 γ +β values instead of 2 α+β . Another method for reducing the required memory size is the ATA method [20] . ...
doi:10.1109/tvlsi.2013.2271696
fatcat:rslwaij4xbbivpogxuo2guptyq
Unified functional decomposition via encoding for FPGA technology mapping
2001
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Functional decomposition has recently been adopted for look-up tabel (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. ...
Consequently, we can handle multiple-output decomposition in the same manner as single-output decomposition. Experimental results show that our algorithms are promising. ...
Thus a more precise estimation of LUT-costs can be derived during functional decomposition in FPGA technology mapping. ...
doi:10.1109/92.924031
fatcat:sq5jrtgcevadhbjrhih36ql7ti
Automated synthesis for asynchronous FPGAs
2005
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05
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We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. ...
peak performance of the FPGA. ...
Currently, we only support balanced decompositions with log 2 N stages. ...
doi:10.1145/1046192.1046214
dblp:conf/fpga/PengFTM05
fatcat:siz6czvw2nfqzpvaxbvqs63sd4
Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures
2012
International Journal of Electronics and Telecommunications
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This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. ...
The model takes into account the type of logic cells or memory blocks used for decomposition process. ...
Several efforts have been made to reduce the DA-LUT size for efficient realization of DA-based designs. Martiez-Peiro et al. ...
doi:10.2478/v10177-012-0046-y
fatcat:qx4zgtfh7ndcfbwgiqjlya4mji
Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal
2018
International Journal of Reconfigurable Computing
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We use a periodic plus smooth decomposition-based approach that was optimized to reduce DRAM access and to decrease 1D FFT invocations. 2D FFTs on FPGAs also suffer from the so-called "intermediate storage ...
We propose a "tile-hopping" memory mapping scheme that significantly improves the bandwidth of the external memory for column-wise reads and can reduce the energy consumption up to 53%. ...
Acknowledgments This work was supported by Japanese Government OIST Subsidy for Operations (Ulf Skoglund) Grant no. 5020S7010020. ...
doi:10.1155/2018/1403181
fatcat:d35dudlaire7noh5eginccozha
A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA
2011
IEEE transactions on nanotechnology
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Finally, we investigate the effectiveness of Shannon-decomposition-based supply gating to reduce static power. ...
Index Terms-Emerging memory technologies, nonvolatile fieldprogrammable gate array (FPGA), Shannon decomposition, spin torque transfer RAM (STTRAM). ...
Due to its nonvolatile nature, the CMOS-STTRAM hybrid FPGA presents an opportunity to extend the same concept for power reduction in FPGA circuits.
1) Hardware Support for Shannon Decomposition: The ...
doi:10.1109/tnano.2010.2041555
fatcat:l5cn4cjskvfw7f7rq45ih47rba
A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[article]
2017
arXiv
pre-print
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Although our overlay provides modest average improvements of 15% to 29% fewer lookup tables for individual finite-state machines, for the more common usage of an overlay supporting different finite-state ...
Although research has introduced overlays for finite-state machines, those architectures suffer from limited scalability and flexibility, which we address with a new overlay architecture using memory decomposition ...
Similarly, the architecture reduces finite-state machine compilation times to tenths of a second and enables potential support for parallel FSMs. ...
arXiv:1705.02732v1
fatcat:ebefhoy6wzaixfg5z4tcsin6uu
Input Variable Partitioning Method for Decomposition-Based Logic Synthesis targeted Heterogeneous FPGAs
2012
International Journal of Electronics and Telecommunications
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The paper presents a method for bound set selection in functional decomposition targeted FPGAs with heterogeneous structure. ...
It is perceived as one of the best logic synthesis methods for FPGAs. However, its practical usefulness for very complex systems depends on efficiency of method used in decomposition calculation. ...
Application of this method for construction of the input variable partition allows reducing the search space to a manageable size while keeping the high-quality solutions in the reduced space.
II. ...
doi:10.2478/v10177-012-0002-x
fatcat:hzsw3as3t5aabiouq54ngre57i
High-Level Design Tools for Floating Point FPGAs
2015
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '15
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The area required for adders and multipliers can
Half 5 10 therefore be reduced by not supporting these exceptions. ...
The floating point compiler mode
enables the user to reduce the area of floating point operations by
removing support for infinity and NaN special values if the user
can guarantee that their application ...
doi:10.1145/2684746.2689079
dblp:conf/fpga/SinghPC15
fatcat:xk2qbx244fczffdbycnfaaedv4
FPGA Latency Optimization Using System-level Transformations and DFG Restructuring
2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
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The results indicate a latency performance improvement of 22% on average versus HLS with the initial DFG for a series of designs mapped to Altera Stratix II devices. ...
The algorithm is time efficient and can be used for fast design space exploration. ...
We demonstrate that TED transformations can directly lead to an average of 22.6% post-mapped improvement in design latency for a set of previously-used HLS benchmarks mapped to Stratix II FPGAs versus ...
doi:10.7873/date.2013.316
dblp:conf/date/Gomez-PradoCT13
fatcat:orwlzfj3rvb3zpdnffrudsadla
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