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An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization
2006
2006 International Conference on Field Programmable Logic and Applications
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However, existing FPGA-based platforms are hampered by physical restrictions limiting the practicability of partial reconfiguration. ...
Using partial dynamic reconfiguration allows the main system to run uninterrupted during the reconfiguration process in addition to the reduced time for the reconfiguration process. ...
The PowerPC on the MotherBoard runs Linux and is the main controller for the whole platform. ...
doi:10.1109/fpl.2006.311364
dblp:conf/fpl/Majer06
fatcat:eunextuzuje3ld3flhgua6rv3m
Reconfigurable Network Stream Processing on Virtualized FPGA Resources
2018
International Journal of Reconfigurable Computing
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With the help of partial reconfiguration technology, network functions on our platform can be configured without affecting other functions on the same FPGA device. ...
The process can happen in the real time of network services and it is able to keep the original function working during the download of partial bitstream. ...
Acknowledgments This work is supported by the EC H2020 dReDBox Project with Grant Agreement no. 687632. ...
doi:10.1155/2018/8785903
fatcat:4onwzouzvffzjnq3jq2hgtxc5e
Customizing virtual networks with partial FPGA reconfiguration
2010
Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures - VISA '10
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The update of hardware-based virtual networks in our system is supported via real-time partial FPGA reconfiguration. ...
Partial reconfiguration allows for 20x faster hardware reconfiguration than a previous approach which migrated hardware virtual networks to software. ...
This work was partially supported by NSF grants CNS-0626618 and CNS-0831940. Dong Yin was supported by China State Scholarship fund CSC-2008629080. ...
doi:10.1145/1851399.1851410
fatcat:2d74urk5pndnbgin2cwbrzmwvq
Customizing virtual networks with partial FPGA reconfiguration
2011
Computer communication review
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The update of hardware-based virtual networks in our system is supported via real-time partial FPGA reconfiguration. ...
Partial reconfiguration allows for 20x faster hardware reconfiguration than a previous approach which migrated hardware virtual networks to software. ...
This work was partially supported by NSF grants CNS-0626618 and CNS-0831940. Dong Yin was supported by China State Scholarship fund CSC-2008629080. ...
doi:10.1145/1925861.1925882
fatcat:yhxsxtbktreijp42heqsrvlx5e
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
2007
2007 IEEE International Parallel and Distributed Processing Symposium
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All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-Cores into the system at run-time. ...
Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. ...
Support for dynamic reconfiguration in operating systems The need for a run-time infrastructure in operating systems to manage and exploit reconfigurable logic is discussed in [9] . ...
doi:10.1109/ipdps.2007.370363
dblp:conf/ipps/RanaSSKKPR07
fatcat:canu4oipnrdshml6yjwtle5kgu
The Erlangen Slot Machine – A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)
2007
it - Information Technology
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For this dynamically reconfigurable computer, the cooperation partner in Braunschweig provides algorithmic solutions, in particular for the optimization of module placements and inter-module communication ...
We introduce a hardware platform called Erlangen Slot Machine (ESM) that has been built in Erlangen within the project ReCoNodes for enabling interdisciplinary research on reconfigurable computing. ...
The reason for the slot or- ganization is that Virtex-II FPGAs only offer partial reconfiguration support for full columns. ...
doi:10.1524/itit.2007.49.3.143
fatcat:ruxrvmb2tndf3hjdg6ixsxqog4
Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA
[chapter]
2015
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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We demonstrate a platform that enables radio designers to build dynamic cognitive radios using the Xilinx Zynq with partial reconfiguration, enabling truly dynamic, low-power, highperformance cognitive ...
While FPGA based SDR platforms do existed, they are difficult to use, requiring significant engineering expertise, and adding dynamic behaviour is even more difficult. ...
It hosts multiple hardware baseband processing chains with support for switching between them and adapting parameters at run-time. ...
doi:10.1007/978-3-319-24540-9_35
fatcat:jxnmucvhwnfgpowrmxvo3ienie
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System
2007
2007 International Conference on Field Programmable Logic and Applications
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On the reconfigurable blade it is desirable that the FPGA devices can be partially reconfigured at run-time. ...
We report our experimental results of the blade doing partial reconfiguration. DPR allows the reconfigurable blade to be a powerful, run-time changeable computing engine. ...
Acknowledgement This work was supported in part by the Semiconductor Research Corporation (2005-HJ-1331). ...
doi:10.1109/fpl.2007.4380710
dblp:conf/fpl/SchleupenLMGNV07
fatcat:mtbh4xbf6bd6zl5czsgwms6ufy
Software Radio and Dynamic Reconfiguration on a DSP/FPGA platform
2004
Frequenz
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of the whole reconfiguration time. ...
Implementation results highlight the benefit of considering a DSP/FPGA platform instead of a multi-DSP platform since the FPGA supports efficiently intensive computation components, which reduces the DSP ...
(i.e., for total and partial reconfiguration of the FPGA). ...
doi:10.1515/freq.2004.58.5-6.152
fatcat:vq5pvlt6uzdltczv2bmdrjtd6e
RUN TIME DYNAMIC PARTIAL RECONFIGURATION USING MICROBLAZE SOFT CORE PROCESSOR FOR DSP APPLICATIONS
2013
International Journal of Research in Engineering and Technology
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Our targeted DSP application is matrix multiplication; we are reconfiguring design by changing partial modules at run time. ...
To change the partial bit stream we interfaces a microblaze Soft processor & using a UART interface.ISE13.1 & PlanAhead is used for partial reconfiguration of FPGA .EDK is used for microblaze soft processor ...
We have implemented the complete design on Xilinx Virtex 6 FPGA .The simulation results are shown for Matrix multiplication. This partial reconfiguration supports to change the design in run time. ...
doi:10.15623/ijret.2013.0212027
fatcat:phf76ylmcrfbtp6bbifqdy4ymy
On-chip and on-line self-reconfigurable adaptable platform: the non-uniform cellular automata case
2006
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
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In this paper we present a platform for evolving CA by exploiting the partial re-configurability of current commercial FPGAs. ...
Our implementation includes an on-chip soft-processor that generates a partial bitstream, reconfigures the FPGA, and computes the fitness. ...
This ICAP allows an on-chip processor to self-reconfigure the FPGA supporting it. Self-reconfigurable platforms modify the system by re-configuring the FPGAs with partial bitstreams. ...
doi:10.1109/ipdps.2006.1639464
dblp:conf/ipps/UpeguiS06
fatcat:ft7uq6pkgvewxgnhegc43xhalu
A Customized Reconfiguration Controller with Remote Direct ICAP Access for Dynamically Reconfigurable Platform
2017
TELKOMNIKA (Telecommunication Computing Electronics and Control)
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As FPGA dynamic partial reconfiguration getting into mainstream, design of reconfiguration controller becomes an active research. ...
Additionally, the proposed reconfiguration controller achieved at least 3.19 Gbps of reconfiguration throughput, which reduces the platform service downtime during dynamic partial reconfiguration. ...
Acknowledgment This work is supported in part by the CREST grant (UTM Vote No. 4B176) and Universiti Teknologi Malaysia matching grant (UTM Vote No. 00M75). ...
doi:10.12928/telkomnika.v15i2.5508
fatcat:o3ged6penres5mlo6xy4znd7hy
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures
2016
2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
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In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental ...
EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low ...
ACKNOWLEDGMENTS The EXTRA project runs from September 2015 till August 2018 and receives funding from the EU Horizon 2020 research and innovation programme under grant No 671653. ...
doi:10.1109/recosoc.2016.7533896
dblp:conf/recosoc/StroobandtVCKBC16
fatcat:3hjjgwqrdzf5notzalewyjdybm
Untethered On-The-Fly Radio Assembly With Wires-On-Demand
2008
2008 IEEE National Aerospace and Electronics Conference
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In systems typified by software defined radio, existing flows for run-time FPGA reconfiguration limit resource efficiency when constructing datapaths. ...
We present the Wireson-Demand framework that allocates a sandbox region in which modules from a library are flexibly placed and interconnected rapidly and autonomously in an embedded platform without vendor ...
Because no vendor tools are used by the framework at run-time, it can be run on any embedded platform with support for C++. ...
doi:10.1109/naecon.2008.4806551
fatcat:pxube23t3zayvmm6olymnukjem
On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure
[chapter]
2014
Lecture Notes in Computer Science
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In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. ...
A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. ...
Implementation of Mapped Memories Using Partial Reconfiguration The Xilinx Virtex 6, used in the MAX3, supports configuration readback and partial reconfiguration of a small portion of the FPGA while the ...
doi:10.1007/978-3-319-05960-0_8
fatcat:5ytuxgo5izbitnxzpox5kf4sji
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