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Managing the Impact of On-chip Temperature on the Lifetime Reliability of Reliably Overclocked Systems

Viswanathan Subramanian, Prem Kumar Ramesh, Arun K. Somani
2009 2009 Second International Conference on Dependability  
Aggressive, but reliable, dynamic clock frequency tuning mechanisms that achieve higher system performance, by adapting the clock rates beyond worst case limits, have been proposed earlier.  ...  Our study shows that a reliably over-clocked system, along with dynamic thermal throttling, achieves around 25% performance improvement, while operating within 355 K.  ...  SPRIT 3 E [9] achieves higher performance in superscalar processors by dynamically varying the operating frequency during run time beyond worst-case limits.  ... 
doi:10.1109/depend.2009.30 fatcat:5ynkzgetyrcnxeh5vqpicwr3ii

Processor Performance Enhancement Using Self-Adaptive Clock Frequency

Sasikala D, M.Ravichandran M.E., Dr.C.S. Ravichandran
2010 International Journal of Computer Applications  
The clock frequency of the processor is generally set to operate below the maximum permissible operating frequency which achieves less than the maximum performance gains.  ...  However, in-fact higher performance gain can be achieved by dynamic overclocking mechanism, which tunes the clock rate beyond the worst case assumptions.  ...  Uht [1] introduces the TEATIME technique which adapts the clock frequency dynamically to enhance the performance and adapt to the system's operating conditions.  ... 
doi:10.5120/780-1104 fatcat:lngttz27pjbx5llmqqvagymtha

Tuning the Pentium Pro microarchitecture

D.B. Papworth
1996 IEEE Micro  
Performance enhancements should come primarily from the microarchitecture and not from clock speed enhancements per se.  ...  applications for the Intel architecture place additional constraints on the design, constraints beyond the purely academic ones of performance and clock frequency We do not have the flexibility to control  ...  Performance enhancements should come primarily from the microarchitecture and not from clock speed enhancements per se.  ... 
doi:10.1109/40.491458 fatcat:cjootody3veltmjtytdo42uuru

Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

P.W. Cook, M. Gupta, V. Zyuban, J. Wellman, A. Buyuktosunoglu, P.N. Kudva, H. Jacobson, S.E. Schuster, P. Bose, D.M. Brooks
2000 IEEE Micro  
Thus, power and performance attributes of a pair (program, machine) can both be enhanced via dynamic adaptation.  ...  Mor recently, Albonesi (see same box) investigated the power-performance trade-offs that can be exploited by dynamically changing the cache sizes and clock frequencies during program execution.  ...  The need for robust power-performance modeling at the microarchitecture level will continue to grow with tomorrow's workload and performance requirements.  ... 
doi:10.1109/40.888701 fatcat:ppinuavlsjf2bouizu2yhbmonm

Runtime-Aware Architectures: A First Approach

2014 Supercomputing Frontiers and Innovations  
processors.  ...  In the last few years, the traditional ways to keep the increase of hardware performance at the rate predicted by Moore's Law have vanished.  ...  superscalar processors performance.  ... 
doi:10.14529/jsfi140102 fatcat:4bh33566cfbz7iylsf2ufppsfa

Fault-Tolerant Computing with Heterogeneous Hardening Modes [chapter]

Florian Kriebel, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Shafique
2020 Embedded Systems  
This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories  ...  We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches.  ...  Another solution is to exploit the dynamic voltage and frequency scaling to generate the dynamic redundancy and voltage scaling with respect to the effects of process variations, application vulnerability  ... 
doi:10.1007/978-3-030-52017-5_7 fatcat:d3wgo4fcvfcldgmhl2hfido5ee

Low Power Multicore Processors for Embedded Systems [chapter]

Fumio Arakawa
2012 Embedded Systems  
However, the scaling has hit the power wall, and frequency enhancement is slowing down.  ...  This means lower performance processors can achieve higher power effi ciency. Therefore, we should make use of the multicore chip with relatively low performance processors.  ...  Each processor core can operate at a different frequency or even dynamically stop the clock to maintain processing performance while reducing the average operating power consumption.  ... 
doi:10.1002/9781118468654.ch1 fatcat:aknopwezfnhy3kyw5mpnmmp7l4

IBM power5 chip: a dual-core multithreaded processor

R. Kalla, B. Sinharoy, J.M. Tendler
2004 IEEE Micro  
With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels.  ...  In this article, we describe the approach we used to improve chip-level performance. Multithreading Conventional processors execute instructions from a single instruction stream.  ...  With that base requirement, we specified increased performance and other functional enhancements of server virtualization, reliability, availability, and serviceability at both chip and system levels.  ... 
doi:10.1109/mm.2004.1289290 fatcat:s5epfknmljfwvkjotdl4n2fcpi

DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors

Hu Chen, Sanghamitra Roy, Koushik Chakraborty
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
To effectively exploit these delay variations, we propose Dynamically Adaptable Resilient Pipeline (DARP)-a series of runtime techniques to boost power performance efficiency and fault tolerance in a pipelined  ...  Using a rigorous circuitarchitectural infrastructure, we demonstrate substantial improvements in the performance (9.4-20%) and energy efficiency (6.4-27.9%), compared to state-of-the-art techniques.  ...  Instead of application driven sensitized path delays, both these schemes use random inputs to drive their clock tuning mechanisms. • DARP: In this scheme, we do dynamic frequency tuning for each benchmark  ... 
doi:10.7873/date.2014.075 dblp:conf/date/ChenRC14 fatcat:yqdyqit6a5ehrdwqkxjry36vxq

Current Methods for Evaluating Performance of Computer Systems

Agbaje M.O, N. Atansuyi, T. Oyelakun
2022 Zenodo  
In this paper, we considered the development trend of the processor performance through computation, storage, and network dimensions with review of the global competition between manufacturers and by extension  ...  Related works in processor performance measurements are reviewed and the consideration of challenges and future developments are enumerated.  ...  . + Valuen×Frequencyn Clock Time (CT) Clock time (CT) is the period of synchronization of circuits in the processor and inversely proportional to the clock frequency, as a case in point, 1 GHz processor  ... 
doi:10.5281/zenodo.6395828 fatcat:d5r5qxtpnzhtdmzmw6vegi373i

Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems

Naga Durga Prasad Avirneni, Viswanathan Subramanian, Arun K. Somani
2009 2009 IEEE/IFIP International Conference on Dependable Systems & Networks  
Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency  ...  For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation  ...  Local Clock Generation Reliable dynamic overclocking technique has been proposed earlier, in [16] , to improve system performance by tuning the clock frequency beyond the conservative worstcase clock  ... 
doi:10.1109/dsn.2009.5270340 dblp:conf/dsn/AvirneniSS09 fatcat:pqo6ov6cm5dfde73zzcqovuh5m

Low-Overhead Core Swapping for Thermal Management [chapter]

Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Tim Sherwood
2005 Lecture Notes in Computer Science  
Our results show that our thermal mechanisms outperform traditional Dynamic Thermal Management (DTM) techniques by reducing the performance hit caused by slowing/swapping of cores.  ...  To combat these trends, we evaluate the thermal efficiency of the microcore architecture, a deeply decoupled processor core with larger structures factored out as helper engines.  ...  Our processor operates at a 5.6 GHz clock frequency. We used the SPEC2000 benchmark set for our experiments.  ... 
doi:10.1007/11574859_4 fatcat:q2ppghtpkvgy5dlnpm6xlimafa

Enhancing the Efficiency of Energy-Constrained DVFS Designs

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Dynamic voltage and frequency scaling (DVFS) is a popular energy reduction technique that allows a hardware design to reduce average power consumption while still enabling the design to meet a high-performance  ...  Index Terms-Context-aware design, dynamic voltage and frequency scaling, lifetime energy reduction, low-power design.  ...  energy efficiency for a dynamically scalable processor.  ... 
doi:10.1109/tvlsi.2012.2219084 fatcat:oziivetnvnfftkbfyukbri5ck4

Recent thermal management techniques for microprocessors

Joonho Kong, Sung Woo Chung, Kevin Skadron
2012 ACM Computing Surveys  
Thermal reliability/security issues cover temperature-dependent reliability modeling, dynamic reliability management (DRM), and malicious codes that specifically cause overheating.  ...  Microarchitectural techniques include both static and dynamic thermal management techniques that control hardware structures.  ...  Clock frequency scaling and voltage/frequency scaling techniques adjust the clock frequency and/or voltage of the microprocessor dynamically.  ... 
doi:10.1145/2187671.2187675 fatcat:bsvvqax2rbftxivi555mzzc7uy

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric

Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh
2010 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture  
This paper proposes FlexCore, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core.  ...  FlexCore takes moderate silicon area and results in far better performance and energy efficiency than software.  ...  We also note that these software implementations are tested on high-performance processors where additional instructions can be hidden by the superscalar and dynamic scheduling techniques.  ... 
doi:10.1109/micro.2010.17 dblp:conf/micro/DengLMSS10 fatcat:htxhhfdrmvfm3lwbqtlditg22i
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