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Intermetallic Cu3Sn as oxidation barrier for fluxless Cu-Sn bonding

H. Liu, K. Wang, K. Aasmundtveit, N. Hoivik
2010 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)  
analyzed based on data acquired in this study and in literature, where various deposition methods lead to different grain size; The influence of temperature ramp rate at the beginning of the bonding process  ...  H.Liu: Cu-Sn intermetallic bonding for 3D MEMS integration 5 Acronyms 3D Three dimensional PoP Package on package ASIC Application-specific integrated circuit PR Photoresist BAR Bulk Acoustic Resonator  ...  VTI has addressed this approach as Chip-on-MEMS, which is based on a combination of wafer-level encapsulation, wafer level packaging (WLP) technology and chip-to-wafer bonding technology.  ... 
doi:10.1109/ectc.2010.5490709 fatcat:jnu6kcj5xvbwhgyzxkg7wfomf4

Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Tanja Braun, Karl-Friedrich Becker, Ole Hoelck, Steve Voges, Ruben Kahle, Marc Dreissigacker, Martin Schneider-Ramelow
2019 Micromachines  
In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors.  ...  Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/mi10050342 pmid:31126083 pmcid:PMC6562530 fatcat:svpuevoojzf2pkzmooc2lz4heu

Security and privacy issues of physical objects in the IoT: challenges and opportunities

Xuanxia Yao, Fadi Farha, Rongyang Li, Ismini Psychoula, Liming Chen, Huansheng Ning
2020 Digital Communications and Networks  
On this basis, a physical object-based security architecture for the IoT is put forward.  ...  Considering the development of IoT technologies, potential security and privacy challenges that IoT objects may face in the pervasive computing environment are summarized.  ...  Zhao Yue et al. presented a novel ASIC self-destruction technology at the chip level by integrating the MEMS metal bridge initiator and the ASIC [77] .  ... 
doi:10.1016/j.dcan.2020.09.001 fatcat:ho7hiqfwwfb55f4j5uejaa36y4

Radiation sensitivity of microelectromechanical system devices

Herbert R. Shea
2009 Journal of Micro/Nanolithography  
A survey of all published reports of radiation effects on MEMS is presented, as well as a summary of techniques that can improve their radiation tolerance.  ...  The sensitivity of microelectromechanical system ͑MEMS͒ devices to radiation is reviewed, with an emphasis on radiation levels representative of space missions rather than of operation in nuclear reactors  ...  of order 1 nm and trace widths of order 60 nm, which is one reason why ICs for use in space are generally based on older technologies with thicker gate oxides and larger features͒.  ... 
doi:10.1117/1.3152362 fatcat:c7cppgeusbgxdaaf5wggcmydk4

TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era

Mahabubul Alam, Mark M. Tehranipoor, Ujjwal Guin
2017 Journal of Hardware and Systems Security  
With the advancement of ubiquitous computing under the hood of Internet of Things (IoT) and Cyber-Physical Systems (CPS), the number of connected devices is expected to grow exponentially in the following  ...  Pervasive sensing is the backbone of any IoT/CPS application. Billions of connected devices each having multiple sensors will lead us to the age of trillion sensors.  ...  In the following subsections, we present a taxonomy of trillion sensors based on applications, technologies, and operating principles of the sensors.  ... 
doi:10.1007/s41635-017-0028-8 dblp:journals/jhss/AlamTG17 fatcat:eelk3nbxvzdivnvgnymnorqnku

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices

Jemmy Sutanto, Sindhu Anand, Chetan Patel, Jit Muthuswamy
2012 Journal of microelectromechanical systems  
In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense,  ...  These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking.  ...  mechanical engineering from Georgia Institute of Technology, Atlanta.  ... 
doi:10.1109/jmems.2011.2171326 pmid:24504168 pmcid:PMC3913265 fatcat:lhfej3pxp5hmfisovwhl4yfur4

A Compact Angular Rate Sensor System Using a Fully Decoupled Silicon-on-Glass MEMS Gyroscope

Said Emre Alper, Yuksel Temiz, Tayfun Akin
2008 Journal of microelectromechanical systems  
dry etching in the silicon-on-glass process.  ...  A patterned metal layer is included at the bottom of the silicon substrate, both as an etch-stop layer and a heat sink to prevent heating-and notching-based structural deformations encountered in deep  ...  The effect of the etch-rate variation becomes essential for the through-etching of a silicon layer located on top of an insulating base.  ... 
doi:10.1109/jmems.2008.2007274 fatcat:ij5tfa57dvaxrody3kw4d4dn5a

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2005 Journal of electronic testing  
This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent.  ...  Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized.  ...  Acknowledgments The authors would like to thank Damien Bretegnier and Vincent Gouin of the Infineon SRAM design group in Sophia-Antipolis for their helpful support.  ... 
doi:10.1007/s10836-005-6146-1 fatcat:3h2bkkeyuzghjebajxgoz4pkbq

Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives [article]

Lois Orosa, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie Kim, Vivek Seshadri (+4 others)
2019 arXiv   pre-print
First, a new Dataplant-based physical unclonable function (PUF) with non-destructive read-out, low evaluation latency, robust responses, resiliency to temperature changes, and data-independent responses  ...  Using a combination of detailed simulations and experiments with 136 real commodity DRAM chips, we show that our Dataplant-based PUF has 1.8x higher throughput than the best state-of-the-art DRAM PUFs.  ...  We customize Ramulator [76] to support all the mechanisms on in-order cores.  ... 
arXiv:1902.07344v2 fatcat:rpfx6htqjfbhtjirzjy76rbbia

An Active Thin-Film Cochlear Electrode Array With Monolithic Backing and Curl

Angelique C. Johnson, Kensall D. Wise
2014 Journal of microelectromechanical systems  
Based on the initial success of these first-generation passive arrays, Bell and Wise went on to create a second generation of active arrays [40] .  ...  The space of the otic bulla roughly 2.5mm by 8mm. A 32-site, 4-channel ASIC was realized in 0.5µm ON Semiconductor technology.  ... 
doi:10.1109/jmems.2013.2288947 fatcat:vgdvzzg7ujcb7mzb7qvgl3gqyq

A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses

Dai Jiang, Andreas Demosthenous, Timothy Perkins, Xiao Liu, Nick Donaldson
2011 IEEE Transactions on Biomedical Circuits and Systems  
The stimulator ASIC was implemented in 0.6-m high-voltage CMOS technology occupying an area of 2.27 mm 2 . The measured performance of the ASIC has been verified using vestibular electrodes in saline.  ...  This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis.  ...  Based on these findings, a variety of prototype vestibular prostheses has been developed.  ... 
doi:10.1109/tbcas.2011.2138139 pmid:23851203 fatcat:3hnjg637gvfm7hhl747jvlcywe

Defense Advanced Research Projects Agency (Darpa) Fiscal Year 2016 Budget Estimates

Department Of Defense Comptroller's Office
2015 Zenodo  
-Define initial concept vehicles based on emerging technologies. -Develop parametric models for evaluating military utility of technologies.  ...  FY 2014 Accomplishments: -Executed a ground-based proof of concept study refining an approach to crew station interfacing. -Initiated development of core crew station technologies.  ... 
doi:10.5281/zenodo.1215366 fatcat:cqn5tyfixjanzp5x3tgfkpedri

Defense Advanced Research Projects Agency (Darpa) Fiscal Year 2015 Budget Estimates

Department Of Defense Comptroller's Office
2014 Zenodo  
warriors with post-traumatic brain injury, stress, or loss of memory (i.e. the Restoring Active Memory (RAM) funding opportunity), as well as new neurotechnology-based capabilities (e.g. the Systems-Based  ...  Also cited under this heading is the proposed DARPA-like funding mechanism to stimulate technology development, which is detailed below.  ...  FY 2014 Plans: -Execute a ground-based proof of concept study refining an approach to crew station interfacing. -Initiate development of core crew station technologies.  ... 
doi:10.5281/zenodo.1215345 fatcat:fjzhmynqjbaafk67q2ckcblj2m

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

Kailiang Chen, Hae-Seung Lee, Charles G. Sodini
2014 2014 Symposium on VLSI Circuits Digest of Technical Papers  
This work presents a scalable Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasound.  ...  The receiver is implemented with a transimpedance amplifier topology and achieves a lowest noise efficiency factor in the literature (2.1 compared to a previously reported lowest of 3.6, in unit of mP  ...  As a technology in its early research phase, it has shown initial success of a 5x5 working array [47] .  ... 
doi:10.1109/vlsic.2014.6858445 dblp:conf/vlsic/ChenLS14 fatcat:qgth3glxzrawxge5s5nithbdri

Design and Validation for FPGA Trust under Hardware Trojan Attacks

Sanchita Mal-Sarkar, Robert Karam, Seetharam Narasimhan, Anandaroop Ghosh, Aswin Krishna, Swarup Bhunia
2016 IEEE Transactions on Multi-Scale Computing Systems  
We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis.  ...  In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker.  ...  Due to this restriction, we propose a statistical approach of iterative self-checking based on the MERO test approach [14] as shown in Fig. 10 .  ... 
doi:10.1109/tmscs.2016.2584052 fatcat:akd6wzxh7fgmric4ibdqxkd5eu
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