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Structural Fault Modelling in Nano Devices [chapter]

Manoj S. Gaur, Raghavendra Narasimhan, Vijay Laxmi, Ujjwal Kumar
2009 Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering  
In this paper we present a model for structural failures in nano-devices. Fault being considered include stuck-at and bridge faults only.  ...  Simulation results indicate that probabilistic TMR model represents bridge and stuck-at-1 faults better while deterministic model is more suited for stuck-at-0 faults.  ...  Introduction Nano-structures are inherently unreliable and this uncertainty stems from low operating energy levels, thermal perturbations/noise, significant quantum effects at nanoscale and high probability  ... 
doi:10.1007/978-3-642-02427-6_2 fatcat:47fkgvzza5dmrlh3iqotqkp2am

CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture

Mohammed Hadifur Rahman
2017 Journal Electrical and Electronic Engineering  
Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel.  ...  Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability.  ...  These uncertainties are the source of faults in nano level. Popular self assembly fabrication processes have probabilistic nature which result in a fairly large percentage of defective devices.  ... 
doi:10.11648/j.jeee.20170506.15 fatcat:z4csd24gtzh55arj4wcjemesaq

Nano-scale fault tolerant machine learning for cognitive radio

Jaakko Peltonen, Mikko A. Uusitalo, Joni Pajarinen
2008 2008 IEEE Workshop on Machine Learning for Signal Processing  
signals • Whole system in nano-scale: minimizes nano/non-nano communication • RBF network parameters are trained and then manufactured into the device Proposed system Frequency-sensitive sensor bank RBF  ...  at each computing unit • Feature extraction: Noise on the frequency sensors and the extracted features • RBF network: Noise on the centroids, spreads, hidden units, wire weights • Structural faults in  ...  signals • • Whole system in nano-scale: minimizes nano/non-nano communication • RBF network parameters are trained and then manufactured into the device Proposed system Frequency-sensitive sensor  ... 
doi:10.1109/mlsp.2008.4685473 fatcat:suvv2mvdobap3bqopdkmswkfmq

Fault tolerance of decomposed PLAs

O. Keren, I. Levin
2010 2010 East-West Design & Test Symposium (EWDTS)  
The paper studies a fault tolerant nano-PLA structure, which is based on implementing an initial FSM in a form of three interacting dense PLAs.  ...  The paper deals with the fault tolerance of finite state machines (FSMs) implemented by nanoelectronic programmable logic arrays (PLAs).  ...  Comparison of Different Fault Models The quality of a fault tolerant Nano PLA were evaluated by considering three criteria: the fault tolerance property, the total area and the total number of devices.  ... 
doi:10.1109/ewdts.2010.5742040 dblp:conf/ewdts/KerenL10 fatcat:n7pdnpkhobedbfz7znlt6euzga

Research on distribution equipment training system based on holographic projection interactive simulation technology

Meng-Chao Ma, Yan Zhang, Guang-Lei Li, Nan-Nan Gao, Jin-Xin Huang, Zhi-Guang Ma, Ling-Ling Shang, Liang-Feng Guo
2017 IOP Conference Series: Earth and Environment  
The system can carry out the training course of distribution automation equipment structure, disassembling and assembling, daily maintenance, operation, and the fault handling.  ...  This paper presents a three-dimensional (3D) interactive simulation training system based on holographic projection technology, nano-touch technology and interactive training mode, which realize the 3D  ...  equipment structure and its faults model, VRay renderer can be used to render device model.  Holographic interactive training courseware.  ... 
doi:10.1088/1755-1315/94/1/012028 fatcat:lmwt6kger5h73dzo53ewvcir4y

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Andras Moritz
2009 Microelectronics Journal  
After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts.  ...  Dezan, et al., Towards a framework for designing applications onto hybrid nano/CMOS fabrics, Microelectron. J (2008),  ...  The topological organization of the nano and microcomponents, including their hierarchical structure in tiles, can also be captured by a model based on this meta-model.  ... 
doi:10.1016/j.mejo.2008.07.072 fatcat:te4h6zgiincqfnngggutvziuia

Design Simulation and Test of Nano Electro Mechanical Switch Based on On-Line Test through Bias super position

Maha Alshmmari, Waleed Khalid Kadhim, Maryam Adnan Al-Ethary
2020 Iraqi Journal of Nanotechnology  
In this work, a comparison between the response of a fault-free system and the system with some failures has been carried out.  ...  The test results showed a decrease in pull-in voltage with increasing overlap area as a result of wear failure mechanism in Nano Switch (NS).  ...  otherwise the device operates with fault.  ... 
doi:10.47758/ijn.vi1.17 fatcat:h7tqowa7vreczht3mjat757vyq

Fault Models and Yield Analysis for QCA-Based PLAs

Michael Crocker, X. Sharon Hu, Michael Niemier
2007 2007 International Conference on Field Programmable Logic and Applications  
Specifically, we analyze a novel, QCA-based, Programmable Logic Array (PLA) structure, develop an implementation independent fault model, discuss how expected defects and faults might affect yield, and  ...  Various implementations of the Quantum-dot Cellular Automata (QCA) device architecture may help many performance scaling trends continue as we approach the nano-scale.  ...  A PLA fault model has been adopted in the context of nanowire crossbars [7] . For MOSFET PLAs, the crosspoint fault model was developed as a more accurate model for PLA faults [15] .  ... 
doi:10.1109/fpl.2007.4380685 dblp:conf/fpl/CrockerNH07 fatcat:fvw2bqyqgvalhexp2o4dh2rfmm

Modified March C-With Concurrency in Testing for Embedded Memory Applications

Muddapu Parvathi
2012 International Journal of VLSI Design & Communication Systems  
March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST  ...  Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests.  ...  HISTORY OF FUNCTIONAL FAULT MODELS For testing purpose the functional fault models are modelled after faults in memories so that functional tests to detect these faults can be used.  ... 
doi:10.5121/vlsic.2012.3504 fatcat:ozjnqyycpvd5jhwj7wuksmtani

Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs

Wenjing Rao, Alex Orailoglu, Ramesh Karri
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Missing nanoelectronics devices at the crosspoints have been observed as a major source of faults in nanoelectronics crossbars.  ...  We investigate in this paper fault masking for crossbar-based nanoelectronics PLAs.  ...  In this paper we focus on the fault tolerance issue for a nano crossbar based PLA structure.  ... 
doi:10.1109/date.2007.364401 dblp:conf/date/RaoOK07 fatcat:zjhc2l3mofgl5bcwanua2464sy

A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Mohammed Hadifur Rahman
2017 Journal Electrical and Electronic Engineering  
Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level.  ...  Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects.  ...  Introduction In nano-electronics the method of fabrication is very diferent. Nano-electronics circuit is a regular structure generated by a stochastic self-assembly process.  ... 
doi:10.11648/j.jeee.20170505.11 fatcat:nxkryckqhjhivobrikkw7ivppq

Towards Nanoelectronics Processor Architectures

Wenjing Rao, Alex Orailoglu, Ramesh Karri
2007 Journal of electronic testing  
structures on the proposed computational model.  ...  For a processor architecture based on the unreliable nanoelectronic devices, fault tolerance schemes are required so as to ensure the basic correctness of any computation.  ...  nano devices.  ... 
doi:10.1007/s10836-006-0555-7 fatcat:vad4japv4bgnzd6wlhzd5oeczy

Relating reliability to circuit topology

Azam Beg, Walid Ibrahim
2009 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference  
These findings can be useful in creating reliability models for arbitrary circuits.  ...  Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks.  ...  A probabilistic single-event upset (SEU) fault model presented by Rejimon and Bhanja [14] employed logic induced fault encoded directed acyclic graph structured probabilistic Bayesian networks.  ... 
doi:10.1109/newcas.2009.5290421 fatcat:7ulxo3n5gnbczkzqbikymjaugy

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

Lei Fang, Michael S. Hsiao
2008 Journal of electronic testing  
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems.  ...  In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered.  ...  These devices differ from CMOS in both structure and functionality, with advantages including smaller dimensions, less power dissipation, greater performance, etc.  ... 
doi:10.1007/s10836-007-5041-3 fatcat:dajq4fxi2naidft2gujinw6f5m

Bilateral Testing of Nano-scale Fault-tolerant Circuits

Lei Fang, Michael Hsiao
2006 Proceedings (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems)  
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems.  ...  In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered.  ...  These devices differ from CMOS in both structure and functionality, with advantages including smaller dimensions, less power dissipation, greater performance, etc.  ... 
doi:10.1109/dft.2006.17 dblp:conf/dft/FangH06 fatcat:s4dpelng4fbnfcjc6jdn5w2z24
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