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Stream Register Files with Indexed Access

N. Jayasena, M. Erez, Jung Ho Ahn, W.J. Dally
10th International Symposium on High Performance Computer Architecture (HPCA'04)  
Applications with less regular data access patterns perform sub-optimally on such architectures. This paper presents a register file for streams (SRF) that allows arbitrary, indexed accesses.  ...  applications with irregular accesses.  ...  size is the number of neighbor records processed per kernel invocation) We will focus on stream register files, but the indexing technique presented is applicable to vector register files as well  ... 
doi:10.1109/hpca.2004.10007 dblp:conf/hpca/JayasenaEAD04 fatcat:ezo5xdumizdhnnlnjzl3zrvyuu

Mobile-Based Video Caching Architecture Based on Billboard Manager [article]

Rajesh Bose, Sandip Roy, Debabrata Sarddar
2015 arXiv   pre-print
Video streaming services are very popular today. Increasingly, users can now access multimedia applications and video playback wirelessly on their mobile devices.  ...  Our work focuses on serving user requests by mobile operators from cached resource managed by Billboard Manager, and transmitting the video files from this pool.  ...  Otherwise, it proceeds with the next step of retrieving the video file from its registered cloud-based nodes. 12.  ... 
arXiv:1507.06946v1 fatcat:bim4ok7ixjhhvh3dilklc35dki

Efficient conditional operations for data-parallel architectures

Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
2000 Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33  
For example, polygon rendering speeds up by a factor of 1.8 with the use of conditional streams.  ...  Conditional streams convert these constructs into data-dependent data movement. This allows data-parallel architectures to efficiently execute applications with data-dependent control flow.  ...  Acknowledgements The authors would like to thank Brian Towles for his help with the experiments, as well as all the other Imagine project members for their contributions to this paper and the project.  ... 
doi:10.1145/360128.360145 fatcat:3ey64huyd5dhvhuart3iwypit4

Dataflow computing with Polymorphic Registers

Catalin Ciobanu, Georgi Gaydadjiev, Christian Pilato, Donatella Sciuto
2013 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)  
Data parallel solutions such as Polymorphic Register Files (PRFs) can potentially accelerate applications by facilitating high speed, parallel access to performance-critical data.  ...  PRFs allow additional control over the registers dimensions, and the number of elements which can be simultaneously accessed by computational units.  ...  Four indirection tables, each with 32 entries, are used to access the iVMX register file.  ... 
doi:10.1109/samos.2013.6621140 dblp:conf/samos/CiobanuGPS13 fatcat:sspqvt6m4zdm5neapom5beygza

Delft-Java dynamic translation

J. Glossner, S. Vassiliadis
1999 Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium  
In addition, for translated instruction streams, we realized a 50% performance improvement for out-of-order execution when compared with in-order execution.  ...  When compared with a realizable stack-based implementation, our approach accelerates a Vector Multiply execution by 3.2x for out-of-order execution with register reanaming and 2.7x when hardware constraints  ...  Every indirect operation accesses the index register file to obtain the last previously allocated register.  ... 
doi:10.1109/eurmic.1999.794446 dblp:conf/euromicro/GlossnerV99 fatcat:nyyluu63pvbctgbapbknytd55y

A unified processor architecture for RISC & VLIW DSP

Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
2005 Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05  
The processor core works as a compiler-friendly MIPSlike core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing  ...  This paper presents a unified processor core with two operation modes.  ...  Similarly, the index i must be even with i+1 implicitly specified. This SIMD instruction needs six register file accesses concurrently (four reads and two writes respectively).  ... 
doi:10.1145/1057661.1057675 dblp:conf/glvlsi/LinCLHCLLJ05 fatcat:sjyh74z7mbhb7pvdsgyrowmcja

A Secured Adaptive HTTP-Based Video Streaming System Using AES Algorithm

Aderonke J. Ikuomola
2019 Journal of Advances in Mathematics and Computer Science  
The distribution server comprises of Content Delivery Network and the Web server which delivers media file and the index files to the client over Hyper Text Transfer Protocol (HTTP).  ...  The server requires a media encoder to converts raw (uncompressed) digital video to a compressed format while the streamer breaks the encoded media into segments and save them as file.  ...  It delivers media file and the index files to the client over HTTP.  ... 
doi:10.9734/jamcs/2019/v34i230217 fatcat:u55fieaayzgqvhykb2z65nmlbi

A loop accelerator for low power embedded VLIW processors

Binu Mathew, Al Davis
2004 Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04  
Each SRAM has an associated stream address generator capable of implementing a variety of addressing modes in conjunction with a shared loop accelerator.  ...  The architecture is extremely useful for generating application specific embedded processors, particularly for processing input data which is organized as a stream.  ...  The stream address generator effectively converts the scratch-pad memory into a vector register file that can operate over complex access patterns and even interleave vectors for higher throughput.  ... 
doi:10.1145/1016720.1016726 dblp:conf/codes/MathewD04 fatcat:fcnyomdcofgdhjvhhrs2chebri

Decoupled access/execute computer architectures

James E. Smith
1984 ACM Transactions on Computer Systems  
Single-instruction-stream versions, both physical and conceptual, are discussed, with the primary goal of minimizing the differences with conventional architectures.  ...  The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  To summarize, the time required to load the address latches for the queue register files is the same as the load address latches for the X register files; the time required to read the files is also the  ... 
doi:10.1145/357401.357403 fatcat:bldhhclgifhjdeza2a2bgsxvne

Decoupled access/execute computer architectures

James E. Smith
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
Single-instruction-stream versions, both physical and conceptual, are discussed, with the primary goal of minimizing the differences with conventional architectures.  ...  The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  To summarize, the time required to load the address latches for the queue register files is the same as the load address latches for the X register files; the time required to read the files is also the  ... 
doi:10.1145/285930.285982 dblp:conf/isca/Smith98d fatcat:rerg34mrpjecpe32m74foppnwm

Decoupled access/execute computer architectures

James E. Smith
1982 SIGARCH Computer Architecture News  
Single-instruction-stream versions, both physical and conceptual, are discussed, with the primary goal of minimizing the differences with conventional architectures.  ...  The main feature of the architecture is a high degree of decoupling between operand access and execution.  ...  To summarize, the time required to load the address latches for the queue register files is the same as the load address latches for the X register files; the time required to read the files is also the  ... 
doi:10.1145/1067649.801719 fatcat:rs7imhyh3fd53bzkn27kskr5cq

Agents and Daemons, automating Data Quality Monitoring operations

Luis I Lopera
2012 Journal of Physics, Conference Series  
Manually operated procedures cannot cope with the constant increase in luminosity, datasets and uptime of the CMS detector.  ...  The main goal of automation is to reduce the operator intervention at the minimum possible level, especially in the area of DQM files management, where long-term archival presented the greatest challenges  ...  However the GUI does not automatically registers the files, as files for the same run/dataset may come with only partial results.  ... 
doi:10.1088/1742-6596/396/5/052050 fatcat:7fgqzvqe5fckbowjajttou6wwa

Data management and transfer in high-performance computational grid environments

Bill Allcock, Joe Bester, John Bresnahan, Ann L. Chervenak, Ian Foster, Carl Kesselman, Sam Meder, Veronika Nefedova, Darcy Quesnel, Steven Tuecke
2002 Parallel Computing  
Our high-speed transport service, GridFTP, extends the popular FTP protocol with new features required for Data Grid applications, such as striping and partial file access.  ...  Our replica management service integrates a replica catalog with GridFTP transfers to provide for the creation, registration, location, and management of dataset replicas.  ...  possible interactions with the number of streams.  ... 
doi:10.1016/s0167-8191(02)00094-7 fatcat:hodirpw6sjad5nn6d62mbk2que

Register Pointer Architecture for Efficient Embedded Processors

JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Similarly, loop unrolling is often required to exploit locality in the register file accesses across iterations because naming registers statically is inflexible.  ...  In this paper, we introduce the Register Pointer Architecture (RPA), which allows registers to be accessed indirectly through register pointers.  ...  file consumes 5% of the total processor power and register file with 64 entries dissipate 47% more power than register file with 16 entries.  ... 
doi:10.1109/date.2007.364659 dblp:conf/date/ParkPBBKD07 fatcat:4gmk2jdkh5artbqhvuzgbbz7m4

Imagine: media processing with streams

B. Khailany, W.J. Dally, U.J. Kapasi, P. Mattson, J. Namkoong, J.D. Owens, B. Towles, A. Chang, S. Rixner
2001 IEEE Micro  
The challenge is supplying them with instructions and data. General-purpose processors that rely on global structures such as large multiported register files to provide  ...  Finally, they don't scale to the numbers of arithmetic units or registers required to support a high ratio of computation to memory access.  ...  The scratch-pad unit is a 256-word register file that executes indexed read and write instructions useful for small table lookups.  ... 
doi:10.1109/40.918001 fatcat:u2pddgyyjra2lgzsvsguvyqddi
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