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A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip

Sebastian Werner, Javier Navaridas, Mikel Luján
2016 ACM Computing Surveys  
Increasing fault rates in current and future technology nodes coupled with on-chip components in the hundreds calls for robust and fault-tolerant Network-on-Chip (NoC) designs.  ...  In this article, we review the vast research efforts regarding a NoC's components, namely, topology, routing algorithm, router microarchitecture, as well as system-level approaches combined with reconfiguration  ...  Therefore, in order to be able to use the superior wormhole switching, routing algorithms have to be designed with this in mind.  ... 
doi:10.1145/2886781 fatcat:sjckf7spajclnf5tculdoim6dm

A framework for adaptive routing in multicomputer networks

John Y. Ngai, Charles L. Seitz
1991 SIGARCH Computer Architecture News  
The performance behavior of the proposed adaptive cut-through framework is studied with stochastic modeling and analysis, as well as through extensive simulation experiments for the 2D and 3D rectilinear  ...  Two convexity-related notions are introduced to characterize the conditions under which our adaptive routing formulation is adequate to provide fault-tolerant routing, with minimal change in routing hardware  ...  In Chapter 3, we study the performance of the proposed adaptive cut-through routing scheme from stochastic modeling and analysis, as well as through extensive simu-lation experiments.  ... 
doi:10.1145/121956.121957 fatcat:ffsmnhjqizautb2rini3orlq5i

Methods for fault tolerance in networks-on-chip

Martin Radetzki, Chaochao Feng, Xueqian Zhao, Axel Jantsch
2013 ACM Computing Surveys  
The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years.  ...  It comes with the downside of the circuit elements' increased susceptibility to failure.  ...  Flooding is the most data intensive of the stochastic communication approaches. In its pure form, each switch copies each received packet to all of its output ports.  ... 
doi:10.1145/2522968.2522976 fatcat:3t4b3rhbgbc2bphjevpkzlpm6u

Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

Akram Ben Ahmed, Abderazek Ben Abdallah
2014 Journal of Parallel and Distributed Computing  
In this paper, we present an efficient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance  ...  RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity.  ...  [39] presented an adaptive and fault-tolerant routing for 3D meshes and tori based on storing at each node a table for routing containing information about destination and the list of intermediate nodes  ... 
doi:10.1016/j.jpdc.2014.01.002 fatcat:4t3hluctovcjzgjrttxlb6m3b4

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead

2014 IEEE transactions on computers  
In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (with no routing tables and using a small logic block in every switch) a deadlock-free  ...  Abstract-In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory  ...  It was also partly supported by the COMCAS project (CA501), a project labelled within the framework of CATRENE, the EU-REKA cluster for Application and Technology Research in Europe on NanoElectronics.  ... 
doi:10.1109/tc.2012.299 fatcat:meujzge3svd3foljscvihnpkm4

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

Evangelia Kasapaki, Jens Sparso, Rasmus Bo Sorensen, Kees Goossens
2013 2013 Euromicro Conference on Digital System Design  
NOCs consist of a switching structure of routers connected by links, with network interfaces (NIs) that connect the processors to the switching structure.  ...  English) Multi-processor architectures using networks-on-chip (NOCs) for communication are becoming the standard approach in the development of embedded systems and general purpose platforms.  ...  I would also like to thank my co-supervisor Martin Schoeberl for his feedback and his encouragement in reaching for the best.  ... 
doi:10.1109/dsd.2013.40 dblp:conf/dsd/KasapakiSSG13 fatcat:yzvmstcvkvgfnbm5wysn2ipray

Performability analysis of Networks-on-Chips [article]

Jie Hou, Universität Stuttgart
2021
The goal of this thesis is to cope with the performance and reliability analysis of NoCs jointly under consideration of faults. This is achieved by the concept of the performability analysis.  ...  The introduced methodology consists of two parts. In the first part, generic Markov modeling of NoCs with consideration of different fault models is proposed.  ...  The model presented by the authors in [27] was able to estimate the communication performance of arbitrary topology wormhole-switched NoCs with virtual channels.  ... 
doi:10.18419/opus-11599 fatcat:7tvsnh2gbjbh3p4a64ffumj2hm

Introduction to Semi-discrete Calculus [article]

Amir Shachar
2022 arXiv   pre-print
The Infinitesimal Calculus explores mainly two measurements: the instantaneous rates of change and the accumulation of quantities.  ...  While it seems to be a special case of the rate (via the derivative sign), this work proposes a separate and favorable mathematical framework for the trend, called Semi-discrete Calculus.  ...  Electrical circuits' Fault Analysis Turning on the switch S in [879] increases the inductor current i L .  ... 
arXiv:1012.5751v8 fatcat:jmezjckexbhordebtjyl6r3w4y

Interconnection systems for highly integrated computation devices

Federico <1978> Angiolini, Luca Benini
2008
The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues.  ...  With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt.  ...  In NoCs, wormhole switching [42] is usually employed to reduce switch buffering requirements and to provide low-latency communication [209] .  ... 
doi:10.6092/unibo/amsdottorato/931 fatcat:d6uz2egvvfd4lgjwvnadzjjdra

Astrophysics in 2004

Virginia Trimble, Markus Aschwanden
2005 Publications of the Astronomical Society of the Pacific  
of old settled ( § 9) and unsettled ( § 10) issues, and some things that happen only on Earth, some indeed only in these reviews ( § § 10 and 11).  ...  of old settled ( § 9) and unsettled ( § 10) issues, and some things that happen only on Earth, some indeed only in these reviews ( § § 10 and 11).  ...  accretion disks, and obscuring tori relative to our line of sight.  ... 
doi:10.1086/429117 fatcat:qwqkgv5icvhbnewnmbzchlzisa