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Static scheduling of multiple asynchronous domains for functional verification

M. Kudlugi, C. Selvidge, R. Tessier
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)  
In this paper, we describe scheduling and synchronization techniques to maintain modeling fidelity for designs with multiple asynchronous clock domains that are mapped to parallel verification systems.  ...  In this paper, we present a general approach to address the parallel verification of designs with multiple asynchronous clock domains.  ...  Conclusions In this paper we have described a new, general approach for dealing with multiple asynchronous clock domains in parallel functional verification systems.  ... 
doi:10.1109/dac.2001.935587 fatcat:5dfl7gg475flhcjdupvxr2ugii

Static schedluing of multiple asynchronous domains for functional verification

Murali Kudlugi, Charles Selvidge, Russell Tessier
2001 Proceedings of the 38th conference on Design automation - DAC '01  
In this paper, we describe scheduling and synchronization techniques to maintain modeling fidelity for designs with multiple asynchronous clock domains that are mapped to parallel verification systems.  ...  In this paper, we present a general approach to address the parallel verification of designs with multiple asynchronous clock domains.  ...  Conclusions In this paper we have described a new, general approach for dealing with multiple asynchronous clock domains in parallel functional verification systems.  ... 
doi:10.1145/378239.379040 dblp:conf/dac/KudlugiST01 fatcat:bbn66wwumvhtdizukjbbuhesb4

Static scheduling of multidomain circuits for fast functional verification

M. Kudlugi, R. Tessier
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Index Terms-Asynchronous circuits, FPGA-based emulation, functional verification, static scheduling.  ...  This paper presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to parallel verification hardware.  ...  Selvidge of Mentor Graphics who was a key technical force in support of this project. They also appreciate the assistance of S. Arole, V. Garg, A. Glaser, S. Krishnamoorthy, and P.  ... 
doi:10.1109/tcad.2002.804086 fatcat:owoc5agfwjg5nicdstivbbnw3y

Modeling methodology for integrated simulation of embedded systems

Akos Ledeczi, James Davis, Sandeep Neema, Aditya Agrawal
2003 ACM Transactions on Modeling and Computer Simulation  
Multiple modeling aspects separate orthogonal concepts. The language also allows the representation of the design space of the application, not just a point solution.  ...  Non-functional requirements are captured as formal, application-specific constraints. MILAN has integrated tool support for design-space exploration and pruning.  ...  For synchronous dataflow models, a static schedule is also generated along with the source code.  ... 
doi:10.1145/778553.778557 fatcat:ybtdhcmjlffdzkavd5x7wk4354

Guest Editors' Introduction: GALS Design and Validation

Mike Kishinevsky, Sandeep K. Shukla, Kenneth S. Stevens
2007 IEEE Design & Test of Computers  
Would they alleviate the need for a GALS approach to some extent or could they be used in the context of multiple clock domains?  ...  The analysis of the schedulability of computation, event acceptance and generation, and so on, can be done using formal Calculus.  ... 
doi:10.1109/mdt.2007.166 fatcat:j4y32mb5t5egxkzly4vlirbggq

Lightweight capability domains

Charles Jacobsen, Muktesh Khole, Sarah Spall, Scotty Bauer, Anton Burtsev
2015 Proceedings of the 8th Workshop on Programming Languages and Operating Systems - PLOS '15  
Despite a number of radical changes in how computer systems are used, the design principles behind the very core of the systems stack-an operating system kernel-has remained unchanged for decades.  ...  Our work on lightweight capability domains (LCDs) develops principles, mechanisms, and tools that enable incremental, practical decomposition of a modern operating system kernel.  ...  Multiple projects attempt to re-implement kernel functionality from scratch in a safer, verification friendly language [9, 25, 28, 34, 54] .  ... 
doi:10.1145/2818302.2818307 dblp:conf/sosp/JacobsenKSBB15 fatcat:wxl2ied63rfatg6oazr7ozh7aa

Trends in functional verification

Harry D. Foster
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
Technical publications often make either subjective or unsubstantiated claims about today's functional verification process-such as, 70 percent of a project's overall effort is spent in verification.  ...  Yet, there are very few credible industry studies that quantitatively provide insight into the functional verification process in terms of verification technology adoption, effort, and effectiveness.  ...  The authors would like to thank Larry and Zachary Wilson (from Wilson Research Group), and Merlyn Brunken (from Mentor Graphics Corporation) for their expertise and guidance in conducting very large industry  ... 
doi:10.1145/2744769.2744921 dblp:conf/dac/Foster15 fatcat:z4udpcuh6var7l7o6kfuio5dw4

FunState-an internal design representation for codesign

K. Strehl, L. Thiele, M. Gries, D. Ziegenbein, R. Ernst, J. Teich
2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph.  ...  It is shown here how properties relevant for scheduling and verification of specification models like boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state  ...  Static Scheduling As a first example we consider a purely static periodic schedule of the synchronous dataflow graph shown on the left-hand side of Fig. 8 for a uni-processor system.  ... 
doi:10.1109/92.931229 fatcat:w3ngg4spgzbdbmgsbzjflvdgde

Formal models for embedded system design

M. Sgroi, L. Lavagno, A. Sangiovanni-Vincentelli
2000 IEEE Design & Test of Computers  
An essential component of a new system Formal Models for Embedded System Design Embedded System Design 2 The authors give an overview of models of computation for embedded system design and propose a new  ...  The system design challenge of at least the next decade is the dramatic expansion of this spectrum of diversity and the shorter and shorter timeto-market window.  ...  The problem of checking if there exists a lossless implementation with bounded queues, which has been solved using static or quasi-static scheduling algorithms for Synchronous Data Flow networks 2 and  ... 
doi:10.1109/54.844330 fatcat:shu576ixcbgijeqof2mzbmtstq

P: Modular and Safe Asynchronous Programming [chapter]

Ankush Desai, Shaz Qadeer
2017 Lecture Notes in Computer Science  
We describe the design and implementation of P, a domain-specific language to write asynchronous event driven code.  ...  verification provided by P.  ...  We would also like to thank him for his enthusiastic adoption of the P programming model.  ... 
doi:10.1007/978-3-319-67531-2_1 fatcat:jhc2xog4hfbqnlpk6n7zc3tzxy

Real-Time Embedded Software Design for Mobile and Ubiquitous Systems

Pao-Ann Hsiung, Shang-Wei Lin, Chao-Sheng Lin
2008 Journal of Signal Processing Systems  
Currently available application frameworks that target at the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for mobile and ubiquitous  ...  The proposed architecture for VERTAF is component-based which allows plug-and-play for the scheduler and the verifier.  ...  What kinds of model can be used for scheduling and verification? 4. What methods are to be used for scheduling and for verification? 5.  ... 
doi:10.1007/s11265-008-0268-5 fatcat:27uddispifgljiywyamnltxdia

Mixed-semantics composition of statecharts for the component-based design of reactive systems

Bence Graics, Vince Molnár, András Vörös, István Majzik, Dániel Varró
2020 Journal of Software and Systems Modeling  
Furthermore, we demonstrate the design and verification functionality of the composition framework by presenting case studies from the cyber-physical system domain.  ...  for formal verification and model-based test case generation.  ...  To view a copy of this licence, visit http://creativecomm ons.org/licenses/by/4.0/.  ... 
doi:10.1007/s10270-020-00806-5 fatcat:cvsn7ay6yzgohm74dq5zsoedse

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  We have successfully run parallelized mpeg3 decoder on the first silicon with several software workarounds, thanks to functional verification environment including system modeling on RTL.  ...  For the design where multiple autonomous entities interact, unexpected racing conditions are created with multiple asynchronous events.  ... 
doi:10.1145/581199.581223 fatcat:x36o4c62hbh7vaozjrpgrwzvte

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  We have successfully run parallelized mpeg3 decoder on the first silicon with several software workarounds, thanks to functional verification environment including system modeling on RTL.  ...  For the design where multiple autonomous entities interact, unexpected racing conditions are created with multiple asynchronous events.  ... 
doi:10.1145/581220.581223 fatcat:ylogpwxrprhafgn6jc2acch3vy

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

Bin Xue, Sandeep K. Shukla
2009 Electronical Notes in Theoretical Computer Science  
In this paper, we present static analysis based framework for such verification.  ...  As Globally Asynchronous and Locally Synchronous (GALS) based System-on-chip (SoC) are gaining importance, a special case of GALS when the global clocking is preserved, but the interconnect delays of multiple  ...  Acknowledgement We thank Kenneth Stevens (University of Utah), Mathew W. Heath (Intel Corp.), Marly E.  ... 
doi:10.1016/j.entcs.2009.07.025 fatcat:bzuxhknqdjg7nhby5qymar44wy
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