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Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information
2009
2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium
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In this paper we present a model that predicts a reasonable bound of the worst-case behavior of data caches during the execution of regular codes without information on the base address of the data structures ...
Most research on static worst-case cache behavior prediction has focused on hard RTS, which need complete information on the access patterns and addresses of the data to guarantee the predicted WCET is ...
Model accuracy A totally safe WCMP prediction in the absence of data address information requires taking a totally pessimistic approach. ...
doi:10.1109/rtas.2009.23
dblp:conf/rtas/AndradeFD09
fatcat:nvmgfxrkuzb5xia2nvnwea2pou
Compositional static instruction cache simulation
2004
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools - LCTES '04
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The module-level analysis parameterizes the data-flow information in terms of potential evictions from cache due to calls containing conflicting references. ...
Scheduling in hard real-time systems requires a priori knowledge of worst-case execution times (WCET). Obtaining the WCET of a task is a difficult problem. ...
This paper presents a novel framework to perform worst-case static cache analysis for direct-mapped instruction caches. ...
doi:10.1145/997163.997183
dblp:conf/lctrts/PatilSM04
fatcat:gpfkatx37vdfnpnjlvenm46gdm
T-CREST: Time-predictable multi-core architecture for embedded systems
2015
Journal of systems architecture
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Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). ...
Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. ...
Acknowledgment This work was partially funded by the European Union's 7th Framework Programme under grant agreement No. 288008: Time-predictable Multi-Core Architecture for Embedded Systems ...
doi:10.1016/j.sysarc.2015.04.002
fatcat:yts4coszkbg7vbes3b4hzdyzui
The worst-case execution-time problem—overview of methods and survey of tools
2008
ACM Transactions on Embedded Computing Systems
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The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems. ...
This problem is hard if the underlying processor architecture has components, such as ...
-A method that can determine the worst-case data-cache performance for data accesses to predictable data structures whose exact location in the address space is statically unknown. ...
doi:10.1145/1347375.1347389
fatcat:lxqtkxuaijcnlb6wy7suu7pdmq
Timing Validation of Automotive Software
[chapter]
2008
Communications in Computer and Information Science
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SymTA/S computes the worst-case response times (WCRTs) of an entire system from the task WCETs and from information about possible interrupts and their priorities. ...
However, the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. ...
The execution time of a task running on one core typically depends on the activities on the other cores. Static worst-case execution time analysis usually assumes the absence of interferences. ...
doi:10.1007/978-3-540-88479-8_8
fatcat:dh2nspuiardefgy3djn4newzgm
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
2009
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Experience with the use of static timing-analysis methods and the tools based on them in the automotive and the aeronautics industries is positive. ...
However, both the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. ...
ACKNOWLEDGMENT The authors would like to thank H. Theiling for suggestions concerning the memory model and the control-flow reconstruction, to S. ...
doi:10.1109/tcad.2009.2013287
fatcat:ok4qpzybefev3h724ayote55gy
Data cache locking for tight timing calculations
2007
ACM Transactions on Embedded Computing Systems
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Our method explores the use of cache partitioning and dynamic cache locking to provide worst-case performance estimates in a safe and tight way for multitasking systems. ...
Detailed information about the number of cache misses and their causes allows us to predict cache behavior and to detect bottlenecks. ...
We are grateful to Thomas Höveken from NEC Electronics (Europe) for supplying information about the NEC controllers. Many thanks to Janne and Jan Gustafsson for reading earlier drafts of this work. ...
doi:10.1145/1324969.1324973
fatcat:gvhsztbomzhi7pmql7onmsbqzm
Time-Predictable Computer Architecture
2009
EURASIP Journal on Embedded Systems
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The proposed architecture is evaluated with implementation of some features in a Java processor. The resulting processor is a good target for WCET analysis and still performs well in the average case. ...
In this paper, we evaluate the issues of current architectures with respect to WCET analysis. Then, we propose solutions for a time-predictable computer architecture. ...
Acknowledgment The author thanks Wolfgang Puffitsch and Florian Brandner for the productive discussions on the topic and suggestions for improving the paper. ...
doi:10.1155/2009/758480
fatcat:4mxu4useyngezo5busxvnx3ize
Minimal placement of bank selection instructions for partitioned memory architectures
2008
ACM Transactions on Embedded Computing Systems
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Our method explores the use of cache partitioning and dynamic cache locking to provide worst-case performance estimates in a safe and tight way for multitasking systems. ...
Detailed information about the number of cache misses and their causes allows us to predict cache behavior and to detect bottlenecks. ...
We are grateful to Thomas Höveken from NEC Electronics (Europe) for supplying information about the NEC controllers. Many thanks to Janne and Jan Gustafsson for reading earlier drafts of this work. ...
doi:10.1145/1331331.1331336
fatcat:bb6vluys7ncojbcw7zdjsiju7e
Message from the Workshop Chair
2005
2005 International Conference on Cyberworlds (CW'05)
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Welcome to the nd international Workshop on Worst-Case Execution Time (WCET) Analysis, a satellite event of the Euromicro Conference on Real-Time Systems. ...
related to object oriented programming models. ¡ On low-level analysis techniques the focus is on modelling timing behaviour of processor features such as cache effects, branch prediction and speculative ...
Acknowledgements Thanks to David Decotigny (IRISA) and Jörn Schneider (Saarland University) for pointing out errors in earlier drafts of this paper. ...
doi:10.1109/cw.2005.66
dblp:conf/cw/XX05a
fatcat:ubjg3eboa5cojl5mrrgucd42ae
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems
2015
ACM Computing Surveys
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However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. ...
One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. ...
In [Vera et al. 2003a ] and [Falk et al. 2007 ], the authors proposed changes in the compiler to extract information regarding the data/instruction access pattern by tasks. ...
doi:10.1145/2830555
fatcat:nckhashqprghfnbcaqqu7vk5vi
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware
[chapter]
2011
Lecture Notes in Computer Science
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An evaluation quantifies the impact of our scratchpad on average case performance. ...
Thus, a predictable behavior is reached that eases a precise timing analysis of the system. We estimate the hardware resources required to implement the dynamic instruction scratchpad for an FPGA. ...
Evaluation of Performance Impact The main contribution of the D-ISP is an improved predictability for instruction fetches: The two-phased execution scheme enforces the absence of instruction and data memory ...
doi:10.1007/978-3-642-19137-4_11
fatcat:zerio5hfibflbbsd2roghkbwia
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach
2017
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017
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Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. ...
In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach. ...
an average performance or worst case performance point of view [5] . ...
doi:10.23919/date.2017.7927000
dblp:conf/date/DerrienPABBDDDF17
fatcat:7d3ac4uwwrb6llwboieuajjuqu
Measurement based WCET Analysis for Multi-core Architectures
2014
Proceedings of the 22nd International Conference on Real-Time Networks and Systems - RTNS '14
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Hence, determination of the Worst Case Execution Time (Wcet) of applications executing on shared memory multi-core processors is hard to estimate. ...
In this paper, we present a technique to measure the Wcet of applications on multi-core architectures using existing measurement based timing analysis tools. ...
The combined trace is depicted in
Figure 4 4 Figure 4: Trace Manipulation
Figure 5 :Figure 6 : 56 Construction of the worst case path considering worst case latency for each cache miss Modified performance ...
doi:10.1145/2659787.2659819
dblp:conf/rtns/ShahCRHK14
fatcat:tts73wn36rh4tgpl3tckyc5uze
Revisiting Cache Block Superloading
[chapter]
2009
Lecture Notes in Computer Science
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In a few cases, we minimally decrease performance compared to the best static size, but best size varies per application, and rarely matches real hardware. ...
We investigate cache blocks of 32-512B, confirming that no fixed size performs well for all applications: differences range from 5-49% between best and worst fixed block sizes. ...
of the best and worst static block sizes in Fig. 2 . ...
doi:10.1007/978-3-540-92990-1_25
fatcat:ehu4b3qejbdu7lt5j5rxaki2xm
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