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A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour

Sander Stuijk, Marc Geilen, Twan Basten
2010 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools  
We present a design flow that takes the dynamic behaviour of applications into account when mapping them onto a multiprocessor platform.  ...  The design flow generates a set of mappings that provide a trade-off in their resource usage.  ...  Time slice allocation The last step of the flow allocates TDMA time slices for all tiles.  ... 
doi:10.1109/dsd.2010.31 dblp:conf/dsd/StuijkGB10 fatcat:vhvrlvveevgqte7btxtbjd4xbe

A Predictable Communication Scheme for Embedded Multiprocessor Systems

Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
2006 2006 IFIP International Conference on Very Large Scale Integration  
A dynamic allocation is more suitable for flexible multiprocessor systems and requires the implementation of a Quality-of-Service (QoS) mechanism.  ...  Networks-on-Chip (NoC) are emerging as a widely accepted alternative for the traditional bus architectures.  ...  allocated for a connection in the connection-oriented scheme.  ... 
doi:10.1109/vlsisoc.2006.313225 dblp:conf/vlsi/HarmanciPIL06 fatcat:alpas2gl4jgm3c5vdx7akcklya

Scheduling Simulations: An Experimental Approach to Time-Sharing Multiprocessor Scheduling Schemes

Swinky Arora, Ankit Arora, Gursharanjit Singh Cheema
2013 International Journal of Computer Applications  
Real time systems that are logically programmed for scientific applications involve frequent job arrivals, thus requires a parallel architecture, so that maximum applications can be executed simultaneously  ...  This must be achieved by workload partitioning & characterization, directs towards the development of Multiprocessor machines, a way to achieve parallel effects.  ...  Long-Term Job Detail Master Queue Fig 3: Simulated-Thread Flow Model Each thread T actually operates like a processing system programmed to process simulated execution flow model as discussed earlier  ... 
doi:10.5120/10512-5476 fatcat:l4ky2o6ekzf6vfn3lracjmkkwq

Page 115 of Journal of Research and Practice in Information Technology Vol. 20, Issue 3 [page]

1988 Journal of Research and Practice in Information Technology  
This is done in two ways: a static allocation and a dynamic allocation.  ...  Ideally the data-flow program graph should be allo- cated to the multiple processing elements of a data-flow machine in a way which maximises the available para- llelism.  ... 

Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures

Shubhendu Sinha, Martijn Koedam, Gabriela Breaban, Andrew Nelson, Ashkan Beyranvand Nejad, Marc Geilen, Kees Goossens
2015 Microprocessors and microsystems  
For these reasons, interest in using multiprocessor platforms for time-critical systems has recently increased.  ...  Applications are statically loaded in their respective partitions.  ...  The compilation flow is illustrated in Figure 6 . Compilation flow for Multiprocessor applications The compilation flow based on the described bundle structure, is illustrated in Figure 7 .  ... 
doi:10.1016/j.micpro.2015.05.017 fatcat:yvqn6pski5cf5bjkabhf7f4fhe

UML design for dynamically reconfigurable multiprocessor embedded systems

Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Jean-Philippe Diguet, Philippe Soulard
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Dynamic reconfiguration has been performed for one co-processor which dynamically implements 3 different computations.  ...  Our approach targets MPSoPC (Multiprocessor System on Programmable Chip) which allows area optimization through partial reconfiguration without performance penalty.  ...  The application execution is defined as a static one since the execution of the tasks are not data or control dependent.  ... 
doi:10.1109/date.2010.5456989 dblp:conf/date/VidalLGDS10 fatcat:256pe3c7xncdlatpeg5y7ftyeu

Indirect VLIW memory allocation for the ManArray multiprocessor DSP

Nikos P. Pitsianis, Gerald G. Pechanek
2003 SIGARCH Computer Architecture News  
to the wide instruction busses usually required in a multiprocessor VLIW DSP.  ...  Abstractm The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManArray family of multiprocessor digital signal processors (DSP) provides a scalable alternative  ...  The authors wish to thank the entire technical staff of BOPS Inc and the Duke University student interns Sanjay Banerjee and Benjamin Strautin for their contributions to this project.  ... 
doi:10.1145/773365.773373 fatcat:x7raspi6czamphv2i4gcskqkau

Predictable Embedded Multiprocessor System Design [chapter]

Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef van Meerbergen
2004 Lecture Notes in Computer Science  
Predictable heterogenous application domain specific multiprocessor systems, which are designed around networks-on-chip, can meet demanding performance, flexibility and power-efficiency requirements as  ...  A multiprocessor system architecture which allows resource budgets allocation and enforcement is described in Section 4.  ...  Such a multiprocessor system is intended for message passing which is a suitable programming paradigm for most signal processing applications.  ... 
doi:10.1007/978-3-540-30113-4_7 fatcat:euzbagceuvfqrfjmnqyzn57qmq

A multiprocessor DSP system using PADDI-2

Roy A. Sutton, Vason P. Srini, Jan M. Rabaey
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
implementations for hardware verification.  ...  The software environment supports a multiprocessor system under development (VGI-1). The software tools and libraries are modular, with implementation dependencies isolated in layered encapsulations.  ...  Software Libraries in Java for Image Processing Our algorithm mapping flow has two paths which branch from the algorithm and re-converge with an algorithm input data stream.  ... 
doi:10.1145/277044.277056 dblp:conf/dac/SuttonSR98 fatcat:ceakqlz3xnah3le3elwlfq2gmm


T.Thillaikkarasi, A. Jagadeesan, K.Duraiswamy
2010 ICTACT Journal on Communication Technology  
This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture incorporating memory allocation.  ...  a memory allocation step which is based on an integer linear programming model.  ...  For this reason, the allocation of the memory blocs major steps in the SoC design flow.  ... 
doaj:b8211922f0a64f35b745d94ebd811555 fatcat:klc3lpzgszcs5j253a7abmdrzy

Baring it all to software: Raw machines

E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe (+1 others)
1997 Computer  
A Baring It All to Software: Raw Machines This innovative approach eliminates the traditional instruction set interface and instead exposes the details of a simple replicated architecture directly to the  ...  Acknowledgments We thank Doug Burger for his incisive technical feedback and his help in condensing this article.  ...  This project is funded by US Defense Advanced Research Projects Agency contract DABT63-96-C-0036 and a National Science Foundation Presidential Young Investigator Award.  ... 
doi:10.1109/2.612254 fatcat:56kdywilqzfiralt33jgiq4aeq

Exploiting the Task-Pipelined Parallelism of Stream Programs on Many-Core GPUs

Shuai MU, Dongdong LI, Yubei CHEN, Yangdong DENG, Zhihua WANG
2013 IEICE transactions on information and systems  
With minor hardware overhead, our techniques orchestrate both task-pipeline and data parallelisms in a unified manner.  ...  By exploiting data-level parallelism, Graphics Processing Units (GPUs) have become a high-throughput, general purpose computing platform.  ...  Therefore, a static allocation of processors is generally not the optimal strategy.  ... 
doi:10.1587/transinf.e96.d.2194 fatcat:ajkjy5a5vrbp5k3sxpqua66hpe

What to Make of Multicore Processors for Reliable Real-Time Systems? [chapter]

Theodore P. Baker
2010 Lecture Notes in Computer Science  
However, not all problems are amenable to parallel decomposition, and for those that are, designing a correct scalable solution can be difficult.  ...  This paper reviews some of what is known about multiprocessor scheduling of task systems with deadlines, including recent advances in the analysis of arbitrary sporadic task systems under fixed-priority  ...  If the primary flows of data are via job objects, the flow of data between cores may be modeled and managed in terms of the flow of jobs.  ... 
doi:10.1007/978-3-642-13550-7_1 fatcat:472cqsnvp5a7fejcnvuhsij27u

Towards Time-Predictable Data Caches for Chip-Multiprocessors [chapter]

Martin Schoeberl, Wolfgang Puffitsch, Benedikt Huber
2009 Lecture Notes in Computer Science  
in a prototype chip-multiprocessor system.  ...  The object header, which contains auxiliary information, is stored on the heap or in a distinct handle area. Class variables. Shared memory area for static variables.  ...  Caches for data where the address is not known statically (e.g., heap allocated data), can only be analyzed when the cache has a very high associativity.  ... 
doi:10.1007/978-3-642-10265-3_17 fatcat:dy2urosnlvbqxmmtuapdas3vna

Automatic Dsp Cache Memory Management And Fast Prototyping For Multiprocessor Image Applications

O. Deforges, Jean Franois Nezan, Mickael Raulet, Fabrice Urban
2006 Zenodo  
A protocol must be followed to ensure no outdated data is accessed [5] . Data involving a dependance on the Data Flow Graph are taken into account by the prototyping tool.  ...  In this way, the generated executives can be seen as an off-line static operating system that is suitable for setting data-driven scheduling, such as signal processing applications.  ... 
doi:10.5281/zenodo.39900 fatcat:skf3b52qkzc5lhrfus3hrw3d74
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