Filters








21,036 Hits in 5.7 sec

Page 1133 of Automation and Remote Control Vol. 21, Issue 12 [page]

1960 Automation and Remote Control  
If, for example, the automaton is constructed from a complete set consisting of delay elements and logic converters, then the additional information on the change on the input is applied to all the delay  ...  From the above it follows that it determines a sequential machine that is equivalent to the specified automaton and in which each group contains only one state.  ... 

A switch level fault simulation environment

V. Krishnaswamy, J. Casas, T. Tetzlaff
2000 Proceedings of the 37th conference on Design automation - DAC '00  
This paper presents a fault simulation environment which accepts pure switch level or mixed switch/RT level descriptions of the design under test.  ...  Switch level fault injection strategies for the stuckat, transition and logic bridge models are presented. A fault simulation algorithm is presented, along with design issues and optimizations.  ...  Acknowledgements We would like to acknowledge the contributions of the following people to the project : Jer-Sheng Chen, Kiran Doreswamy, Ajaya Durg, Trey Jackson, Mandar Joshi, Manpreet Khaira, Dennis  ... 
doi:10.1145/337292.337777 dblp:conf/dac/KrishnaswamyCT00 fatcat:wi3afjrnazdbfffxsifld2642a

Abstracts of Current Computer Literature

1969 IEEE transactions on computers  
Sequential Machines 7126 Method for Determining Feedback Partitions for Sequential Machines from State Tables 7130 Realization of Sequential Machines with Threshold Elements 7131 Synthesis of Sequential  ...  Incomplete Sequential Machines 7125 Code Assignment to the States, Inputs and Outputs of Sequential Machines Based on Threshold Logic 7131 Infinite Linear Sequential Machines 7133 Generation of  ... 
doi:10.1109/t-c.1969.222584 fatcat:5xs4k4tnxzesrhzluh73ldlmy4

Chip-level soft error estimation method

H.T. Nguyen, Y. Yagil, N. Seifert, M. Reitsma
2005 IEEE transactions on device and materials reliability  
It reviews the impact of logical and architectural filtering on SER calculations and focuses on the structural filtering of soft radiation events by nodal timing mechanisms.  ...  This paper gives a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs.  ...  The first case involves a strike occurring directly in sequentials holding the machine state, shown as a strike in the latch in the upper right corner of Fig. 1 .  ... 
doi:10.1109/tdmr.2005.858334 fatcat:vydxo7zl7rdbxlunc4q365g2wm

Abstracts of Current Computer Literature

1969 IEEE transactions on computers  
with Constrained Line Delays 6909 Synthesis of Linear Sequential Machines with Unspecified Outputs 6910 Effect of Memory Elements on Feedback in Sequential Machines 6911 State Assignment in Pulse Sequential  ...  In this paper the possibility of removing in synchronous sequential machines some of the delay elements which store the internal state is discussed.  ... 
doi:10.1109/t-c.1969.222770 fatcat:3u7q7ac3b5hx5fdffcemcrpsay

Constraint extraction for pseudo-functional scan-based delay testing

Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
logic.  ...  In this paper, we use a SAT solver to extract a set of functional constraints which consists of illegal states and internal signal correlation.  ...  Some of the functional constraints involve illegal states (i.e. unreachable states) in a sequential circuit.  ... 
doi:10.1145/1120725.1120797 dblp:conf/aspdac/LinLYC05 fatcat:uwap5umn5vgatjpoefq3l35obe

Timing optimization of multiphase sequential logic

K.A. Bartlett, G. Borriello, S. Raju
1991 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
it whenever a logic either the block has satisfied its goal delay or no move is made across one of its elements.  ...  Primary output and propagation delay of any latches on the inputs of internal state logic is placed in block whose end this path determine the time between the rising phase is the phase,.during which the  ... 
doi:10.1109/43.62791 fatcat:7di3tpamozdrlkqwhd5cay5n5a

Asynchronous Digital Circuit Design using Noise-Driven Stochastic Gates

Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura
2014 IEICE Proceeding Series  
These systems exhibit hysteresis; this property is crucial, because it ensures the stability of all logic states.  ...  Moreover, the application of an external bias, allows the selection of logic operation.  ...  This feedback must contain the delay elements whose delay time is sufficient large to compensate for the internal delays.  ... 
doi:10.15248/proc.2.507 fatcat:fw2iri7s4nfvpalcvfejpvcf2m

Cellular Synthesis of Synchronous Sequential Machines

S.C. Hu
1972 IEEE transactions on computers  
-(all successors of t.). J J 8. If #(Tj+1) = 0, go to step 11; otherwise go to step 9. 9, Find R. = -r ,+ (all successors of t.). 3+1 J J 3 1 0. j = j+1, go to step 6.  ...  machines by slight modifications--addition of delay elements.  ...  All delay elements are assumed to be unit delay elements in our study.  ... 
doi:10.1109/t-c.1972.223513 fatcat:cukpw5mybjdhpive7iiizcbfxy

Sequential hardware Trojan: Side-channel aware design and placement

Xinmu Wang, Seetharam Narasimhan, Aswin Krishna, Tatini Mal-Sarkar, Swarup Bhunia
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
In particular, we illustrate design and placement of sequential hardware Trojans, which are rarely activated/observed and incur ultralow delay/power overhead.  ...  It is shown that efficient design and placement of sequential Trojan would incur extremely low side-channel (power, delay) signature and hence, can easily evade both postsilicon validation and DFS (e.g  ...  For example, the Trojan state machine in Fig. 4 reuses the transition conditions of the original FSM, whose consecutive occurrence is an extremely rare event in state S 4 .  ... 
doi:10.1109/iccd.2011.6081413 dblp:conf/iccd/WangNKMB11 fatcat:r2umb4pmsbdsxge3da2wb7ljdq

The application of parity checks to an arithmetic control

C. P. Disparte
1970 Proceedings of the November 17-19, 1970, fall joint computer conference on - AFIPS '70 (Fall)  
Using a special pattern detecting circuit An auxiliary sequential machine is designed which repeats a portion of the larger sequential machine's states in parallel.  ...  As shown in its flow chart, this logic realizes the sequential energization A A gA gAr B B gB gBr C C In this type of logic, the quiescent state of the memory elements is the "0" state and thus the NAND  ... 
doi:10.1145/1478462.1478474 dblp:conf/afips/Disparte70 fatcat:mvh7vgsvqngalp7k2guic4wnhe

Inside simulation software

Thomas J. Schriber, Daniel T. Brunner
1996 Proceedings of the 28th conference on Winter simulation - WSC '96  
Topics include discrete-event systems and modeling: entities, resources and operations~simulation runs~entity statesẽ ntity lists~and entity-list management.  ...  The paper concludes with several examples of "why it matters" for modelers to know in fine detail how their simulation software works. (This paper is an updated version of an identically named  ...  ACKNOWLEDGMENTS Much of the information in the original yersion of this paper was derived from conversations \vith sofuvarevendor personnel.  ... 
doi:10.1145/256562.256566 fatcat:o4vwohyww5dg5p7vn7e3uhldk4

Inside simulation software

Thomas J. Schriber, Daniel T. Brunner
1995 Proceedings of the 27th conference on Winter simulation - WSC '95  
Topics include discrete-event systems and modeling: entities, resources and operations~simulation runs~entity statesẽ ntity lists~and entity-list management.  ...  The paper concludes with several examples of "why it matters" for modelers to know in fine detail how their simulation software works. (This paper is an updated version of an identically named  ...  ACKNOWLEDGMENTS Much of the information in the original yersion of this paper was derived from conversations \vith sofuvarevendor personnel.  ... 
doi:10.1145/224401.224441 fatcat:gvc7eguk2jhgdphzdpcjqsbqs4

State assignments for reducing the number of delay elements in sequential machines

G.B. Gerace, G. Gestri
1967 Information and Control  
It has been previously shown that internal state assignments can be used for reducing the number of combinational elements in sequential machines.  ...  In this paper it is shown that state assignments can also be employed for reducing the number of delay elements in such machines.  ...  Consider a sequential machine whose output state depends only on the present state. We shall say that the realization of this Fig. 5 .  ... 
doi:10.1016/s0019-9958(67)90296-3 fatcat:rukval7yjfbuvlb2f5c2rkymtu

Accumulators: New logic variable abstractions for functional languages

Keshav Pingali, Kattamuri Ekanadham
1991 Theoretical Computer Science  
We propose a generalization of logic variables called accumulators which are eminently suited for incorporation into functional languages.  ...  on combining the functional and logic programming paradigms.  ...  Notice that the evaluation of the expression A +S is automatically delayed until the command A+67 takes effect. E-structures [4] are simply arrays whose elements are the logic variables described ve.  ... 
doi:10.1016/0304-3975(91)90191-4 fatcat:zt53cptdnbgxfjx6nbb6gs5wuu
« Previous Showing results 1 — 15 out of 21,036 results