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StatCache: A probabilistic approach to efficient and accurate data locality analysis

E. Berg, E. Hagersten
IEEE International Symposium on - ISPASS Performance Analysis of Systems and Software, 2004  
The widening memory gap reduces performance of applications with poor data locality. Therefore, there is a need for methods to analyze data locality and help application optimization.  ...  In this paper we present Stat-Cache, a novel sampling-based method for performing data-locality analysis on realistic workloads.  ...  Acknowledgment We would like to thank Oskar Grenholm for assistance on the instrumentation tool, Allan Gut for valuable comments on the mathematical content and Mathias Spjuth for providing the traces.  ... 
doi:10.1109/ispass.2004.1291352 dblp:conf/ispass/BergH04 fatcat:ljjhl5ngdzgnvayfrnsryaz2ym

Multigrid and Gauss-Seidel smoothers revisited

Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren
2006 Proceedings of the 20th annual international conference on Supercomputing - ICS '06  
Efficient solutions of partial differential equations require a match between the algorithm and the underlying architecture.  ...  Running our smoother on a 32-thread UltraSPARC T1 (Niagara) SMT/CMP and a simulated 32-way CMP demonstrates the communication cost of our algorithm to be low on such architectures.  ...  The tool uses a probabilistic approach that makes it possible to compute the cache miss ratios of any cache size from sparse data samples collected during a single run 1 .  ... 
doi:10.1145/1183401.1183423 dblp:conf/ics/WallinLHH06 fatcat:b6cvzegnzba63crc46kpkur3bq

A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis [article]

Cheng-Lin Tsai, Ren-Song Tsay
2021 arXiv   pre-print
Our key contribution is to generalize the reuse distance analysis method and develop an effective and practical cache design optimization approach.  ...  In this paper, we propose a practical and effective approach allowing designers to optimize multi-level cache size at the early system design phase.  ...  To effectively shorten reuse distance computation time, StatCache [6] proposed to compute only on sampled partial memory access sequence with a sampling rate as low as 10 -4 and adopted a probabilistic  ... 
arXiv:2109.04614v1 fatcat:olt7fnzmsrferas2w4yuzhynz4

Program locality analysis using reuse distance

Yutao Zhong, Xipeng Shen, Chen Ding
2009 ACM Transactions on Programming Languages and Systems  
This article addresses the analysis problem at the program level, where the size of data and the locality of execution may change significantly depending on the input.  ...  accesses to a given location.  ...  John Mellor-Crummey and Rob Fowler provided access to Rice Alpha clusters.  ... 
doi:10.1145/1552309.1552310 fatcat:hk4yld6lsvcxxf5gpjvp2phssa

Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence

Ming Ling, Xiaoqian Lu, Guangmin Wang, Jiancong Ge
2021 IEEE Access  
[3] provided a probabilistic model to find the merged stack distance profiled from the locality information of two individual threads.  ...  cycle-accurate simulations to obtain the lower-level cache traces.  ... 
doi:10.1109/access.2021.3053350 fatcat:4nt7ucqlpveotl7hsscjhimnue

Directed Statistical Warming through Time Traveling

Nikos Nikoleris, Lieven Eeckhout, Erik Hagersten, Trevor E. Carlson
2019 Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture - MICRO '52  
Sampling is a widely used methodology to speed up workload analysis and performance evaluation by extrapolating from a set of representative detailed regions.  ...  CCS CONCEPTS • Computing methodologies → Modeling and simulation; • Hardware → Analysis and design of emerging devices and systems; • Computer systems organization → Serial architectures.  ...  This work was also supported by a Start-up Grant from the National University of Singapore (NUS).  ... 
doi:10.1145/3352460.3358264 dblp:conf/micro/NikolerisEHC19 fatcat:ivhie6ytoree7mpltj4gk4v63a

Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence [article]

Ming Ling, Xiaoqian Lu, Guangmin Wang, Jiancong Ge
2020 arXiv   pre-print
In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache under multi-core scenarios.  ...  To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely accepted in modern processors.  ...  [3] provided a probabilistic model to find the merged stack distance profiled from the locality information of two individual threads.  ... 
arXiv:2007.11195v2 fatcat:dhapkq5yq5bubdvh3rqvaw6oey

Modeling cache performance beyond LRU

Nathan Beckmann, Daniel Sanchez
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
We present a new probabilistic cache model designed for high-performance replacement policies.  ...  Finally, we present a case study showing how to use the model to improve shared cache performance.  ...  This work was supported in part by NSF grant CCF-1318384 and a grant from the Qatar Computing Research Institute.  ... 
doi:10.1109/hpca.2016.7446067 dblp:conf/hpca/BeckmannS16 fatcat:pcbfqiafrba5fhrjqup7pituga