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Cache-only memory architectures

F. Dahlgren, J. Torrellas
1999 Computer  
If the pro- gram's memory access patterns are too complicated for  the software to understand, individual data structures  may not end up being placed in the memory module of  the node that access  ...  Unlike in a conventional  CC-NUMA architecture, in a COMA, every shared- memory module in the machine is a cache, where each  memory line has a tag with the line's address and state.  As a processor  ...  The line has simply been  displaced from the AM in the home node.  Because Flat COMA does not rely on a hierarchy to  find a block, it can use any high-speed network.  Simple COMA  A design  ... 
doi:10.1109/2.769448 fatcat:ozadfmvoyne5jczmnm42x4ukza

Cache-coherent distributed shared memory: perspectives on its development and future challenges

J. Hennessy, M. Heinrich, A. Gupta
1999 Proceedings of the IEEE  
Cache coherence allows such architectures to use caching to take advantage of locality in applications without changing the programmer's model of memory.  ...  We review the key developments that led to the creation of cache-coherent distributed shared memory and describe the Stanford DASH Multiprocessor, the first working implementation of hardware-supported  ...  Figure 8 shows the time to access different levels in the memory hierarchy for DASH [Len92] .  ... 
doi:10.1109/5.747863 fatcat:koqfmkqdibaylcxfiheb33bwly

Excel-NUMA: toward programmability, simplicity, and high performance

Zheng Zhang, M. Cintra, J. Torrellas
1999 IEEE transactions on computers  
The idea is to exploit the fact that, after a memory line is written and cached, the storage that kept the line in memory is unutilized.  ...  Simulations of Splash2 applications show that EX-NUMA outperforms CC-NUMA and Flat-COMA in every single application and eliminates most of the conflict misses.  ...  time to access the remote cache in NUMA-RC as the attraction memory in Flat-COMA.  ... 
doi:10.1109/12.752667 fatcat:wb25cqjjqjbajieqy37rdejjwy

An efficient and scalable approach for implementing fault-tolerant DSM architectures

C. Morin, A.-M. Kermarrec, M. Banatre, A. Gefflaut
2000 IEEE transactions on computers  
The implementation of the protocol in a COMA architecture has been evaluated by simulation. The protocol has also been implemented in an SVM system on a network of workstations.  ...  This approach can be applied to both Cache Only Memory Architectures (COMA) and Shared Virtual Memory (SVM) systems.  ...  The work presented in this paper was conducted while all authors were with IRISA, Rennes, France. This work was supported by DRET (research contract number 93.34.124.00.470.75.01).  ... 
doi:10.1109/12.859537 fatcat:4b5ka7itibai7mzqplpg56rcey

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
The 1990s will be the era of scalable computers. By giving up uniform memory access, computers can be built that scale over a range of several thousand.  ...  The parameters that determine these structures and their utility include: whether hardware (a multiprocessor) or software (a multicomputer) is used to maintain a distributed, or shared virtual memory (  ...  The CS-2 exhibited linear speed-up on Oracle apps. Fujitsu's VPPSOO supercomputer.  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

Virtual memory on data diffusion architectures

Jorge Buenabad-Chávez, Henk L Muller, Paul W.A Stallard, David H.D Warren
2003 Parallel Computing  
A b s t r a c t Data diffusion architectures (also known as COMA machines) are scalable multiprocessors that provide a shared address space on top of distributed main memory.  ...  This property is possible due to the associative organisation of main memory, which in effect decouples each address and its data item from any physical location.  ...  Acknowledgements It is a pleasure to thank the people who made possible the completion of this work. The British Council, CINVESTAV 1 , CONACyT 2 and SEP 3 provided the necessary funds.  ... 
doi:10.1016/s0167-8191(03)00088-7 fatcat:gsvwk6bp2na2zbturcplocdpr4

Evaluating and designing software mutual exclusion algorithms on shared-memory multiprocessors

X. Zhang, Y. Yan, R. Castaneda
1996 IEEE Parallel & Distributed Technology Systems & Applications  
Like CC-NUMA, in COMA each processor has a cache and a designated portion of the global shared memory. However, COMA augments the memory of each processor to act as a large cache.  ...  time bound on the instruction speed or on the execution time of the CS.  ... 
doi:10.1109/88.481663 fatcat:rdpg2oxmofas5cdeu5btuzhox4

The KSR1

E. Rosti, E. Smirni, T. D. Wagner, A. W. Apon, L. W. Dowdy
1993 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems - SIGMETRICS '93  
Acknowledgements The helpful information, criticisms, and suggestions provided by Tom Dunigan, Rich Stirling, and Jim Rothnie have significantly improved this paper.  ...  Both the actual system curve and that from the analytic model are flat up to 25 readers (and 5 writers).  ...  Architectural Overview of the KSRl System Hardware The general KSR architecture is a multiprocessor system composed of a hierarchy of rings.  ... 
doi:10.1145/166955.166985 dblp:conf/sigmetrics/RostiSWAD93 fatcat:achxjhmjm5duxepcc7kropuini

Optimum Binary Search Trees on the Hierarchical Memory Model [article]

Shripad Thite
2008 arXiv   pre-print
The Hierarchical Memory Model (HMM) of computation is similar to the standard Random Access Machine (RAM) model except that the HMM has a non-uniform memory organized in a hierarchy of levels numbered  ...  memory hierarchy.  ...  The speed-up technique in this section is used to improve the running time of the standard dynamic programming algorithm to compute optimum BSTs.  ... 
arXiv:0804.0940v1 fatcat:7bjiignjqve2dkh6zcc6dbwueq

Supporting Microthread Scheduling and Synchronisation in CMPs

Ian Bell, Nabil Hasasneh, Chris Jesshope
2006 International journal of parallel programming  
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems.  ...  This paper shows scalability in performance, power and most importantly, in silicon implementation, the main contribution of this paper.  ...  project, which has been funded in their GLANCE program, project number: 600.643.000.05N07.  ... 
doi:10.1007/s10766-006-0017-y fatcat:w7l3s4r6mnevpjzpuv5lhmebfm

Cache-Only Memory Architecture

Rahul Yadav, Mukul Yadav, Shadab Anwar
unpublished
A Cache-Only Memory design (COMA) may be a sort of cache-coherent non-uniform access (CC-NUMA) design. not like in a very typical CC-NUMA design, in a COMA, each shared-memory module within the machine  ...  Effectively, every shared-memory module acts as a large cache memory, giving the name COMA to the design.  ...  Because Flat COMA does not rely on a hierarchy to find a block, it can use any high-speed network. 2.3Simple COMA A design called Simple COMA (S-COMA) [10] transfers some of the complexity in the AM  ... 
fatcat:u2v4hv4f5nh27atfidu57ayf2i

High-performance computing systems: Status and outlook

J. J. Dongarra, A. J. van der Steen
2012 Acta Numerica  
We review the different ways devised to speed them up, both with regard to components and their architecture.  ...  This article describes the current state of the art of high-performance computing systems, and attempts to shed light on near-future developments that might prolong the steady growth in speed of such systems  ...  In S-COMA systems the cache hierarchy of the local nodes is extended to the memory of the other nodes.  ... 
doi:10.1017/s0962492912000050 fatcat:n6yodkox5zb6xmlep6gvayud2m

Enhancing memory use in Simple Coma: Multiplexed Simple Coma

S. Basu, J. Torrellas
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture  
Scalable shared-memory multiprocessors  ...  Acknowledgments We thank the referees and members of the I-ACOMA group for their valuable feedback. Josep Torrellas is supported in part by a n NSF Young Investigator Award.  ...  Architectures Simulated We model Flat Coma, Simple Coma, and Multiplexed Simple Coma machines with similar memory hierarchies. The default parameters are as follows.  ... 
doi:10.1109/hpca.1998.650555 dblp:conf/hpca/BasuT98 fatcat:sqvucs4sfff4lgb4lzvg3n35o4

Computer architecture : from the orthogonal valuation of names up to structuring the N-stream

Jean-Louis Lafitte, Charles-André Heritier, Bastien Chopard
2002
On Structured Data Handling in Parallel Processing Cet article présente les premiers aspects du modèle que nous proposons et a été publié dans les ACM Computer Architecture News en décembre 1995.  ...  linear flat way of current memory addressing scheme.  ...  the given memory hierarchy).  ... 
doi:10.13097/archive-ouverte/unige:203 fatcat:iwfub4tfmngxtem7zkuachah2m

Relevance of time‐varying properties of the first formant frequency in vowel representation

Maria‐Gabriella Di Benedetto
1985 Journal of the Acoustical Society of America  
The first is a roughness parameter R which is equal to the sea wave height measured in airborne sound-speed wavelengths.  ...  In order to enhance the effect of bottom interaction, a Summer Sargasso Sea soand-speed profile was used.  ...  This laboratory facility speeds up the tedious and routine data taking chores of the experiment and frees up time for discussion of the physics.  ... 
doi:10.1121/1.2023018 fatcat:3lbckbce2rglzj7zx3fp4nhiui
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