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Razor

Todd Austin
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
A metastability-tolerant comparator then validates latch values sampled with the fast clock.  ...  Analyses of a fullcustom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to  ...  [1] Circuit-level Speculation employs logic components that operate at two speeds, a fast typical speed and a slower atypical multi-cycle speed.  ... 
doi:10.1145/1150343.1150348 dblp:conf/sbcci/Austin06a fatcat:ts3b7k46kvf7hbk6wicbxi3d7q

Error Estimation and Error Reduction with Input-Vector Profiling for Timing Speculation in Digital Circuits

Xiaowen Wang, William H. Robinson
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
A novel approach was proposed in [10] that isolated the failing path to avoid timing errors caused by process variation for fabricated chips.  ...  It also contains cells with different versions (multi-voltage, multi-threshold, etc.) for low power designs.  ...  Comparison Of Error Estimation vs, Error Checking Results According to the error estimation method introduced in Chapter V, there are error count estimation results for all clock frequencies.  ... 
doi:10.1109/tcad.2018.2808240 fatcat:rfrozu53jjd5pntinkjfieklpq

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Xiaoyao Liang, David Brooks
2006 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
We find that 23% mean frequency improvement with an average IPC loss of 3% (and never exceeding 5% for worst case chips) is possible for the 65nm technology node by properly adopting the proposed schemes  ...  Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors  ...  With random variations, it is possible to cancel out the random delay variation through borrowing.  ... 
doi:10.1109/micro.2006.37 dblp:conf/micro/LiangB06 fatcat:jupdcorr2jegfcy4qyyyrnckky

Snake: An asynchronous pipeline for ultra-low-power applications

Zhi-jiu Zhu, Yi Yu, Xu Bai, Shu-shan Qiao, Yong Hei
2019 IEICE Electronics Express  
Voltage scaling is an effective technique for ultra-low-power applications.  ...  However, PVT variation degrades the robust of traditional synchronous pipelines severely when voltage scales into the sub-threshold region.  ...  He adds an extra delay to the control paths that make the latches opaque, thus widening the capture window and improving the ability to capture data delayed by random PVT variation.  ... 
doi:10.1587/elex.16.20190293 fatcat:p3qifhbayvbq3fdj3i3pptabxm

Performance Analysis of Timing-Speculative Processors

Omid Assare, Rajesh Gupta
2021 IEEE transactions on computers  
I am grateful for the freedom I had to explore and change direction and the opportunity to learn and practice independent thinking. It has been an honor to work under his supervision.  ...  For each α ∈ I, let X α be a Bernoulli random variable with p α = Pr(X α = 1) > 0. Let W = ∑ α∈I X α , and let Z be a Poisson random variable with EZ = EW = λ < ∞.  ...  In a pipeline with S stages, the probability of failing paths being sensitized by the Nth execution reduces as N is increased and reaches zero for N = S + 1.  ... 
doi:10.1109/tc.2021.3051877 fatcat:nkkie5fnx5hybmnjaf52qux36y

Design and test strategies for microarchitectural post-fabrication tuning

Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks
2009 2009 IEEE International Conference on Computer Design  
This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation.  ...  The testing cost for the proposed framework is low, usually converging with fewer than two rounds of tests.  ...  While it is difficult to directly measure the random variation, statistical timing analysis provides a framework for reasoning about their impact.  ... 
doi:10.1109/iccd.2009.5413170 dblp:conf/iccd/LiangLWB09 fatcat:zmqfw7iflndzzbqu3x5s6fr4cm

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

Dac Pham, Atsushi Kameyama, John Keaty, Bob Le, Sang Lee, Tuyen Nguyen, John Petrovick, Mydung Pham, Juergen Pille, Stephen Posluszny, Mack Riley, Hans-Werner Anderson (+11 others)
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
transistor level simulation for detailed analysis.  ...  Key features of this methodology are broad optimization with fast rule-based analysis engines using macrolevel abstraction for constraints propagation up/down the design hierarchy, coupled with accurate  ...  For timing critical paths, a high-performance latch (HPL) [5, 6] was designed which combines a wide mux (up to 10-way), relying on a dynamic NOR gate, with a set-reset latch ( fig. 5 ).  ... 
doi:10.1145/1118299.1118497 fatcat:ijuxxmwlyba7neqnj7fdnp26ee

Enabling system-level modeling of variation-induced faults in networks-on-chips

Konstantinos Aisopos, Chia-Hsin Owen Chen, Li-Shiuan Peh
2011 Proceedings of the 48th Design Automation Conference on - DAC '11  
However, these evaluations assume random fault distributions, which result in 52%-81% inaccuracy.  ...  Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated.  ...  Nigel advised us to combine static timing analysis tools with circuit-level tools in our simulation infrastructure. Tushar Krishna designed our baseline RTL, based on [9] .  ... 
doi:10.1145/2024724.2024931 dblp:conf/dac/AisoposCP11 fatcat:is4biycxjja5xinov2jfrvaehq

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno
2015 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combining the Razor principle with stoppable clocks in a GALS setting.  ...  Index Terms-digital circuits, low power design, high speed integrated circuits.  ...  Delay buffers are required for those paths which fail to meet this minimum path delay constraint.  ... 
doi:10.1109/tcsi.2014.2365878 fatcat:sodgnbqwbnfkvfm42ysmvo32jq

Mitigating random variation with spare RIBs: Redundant intermediate bitslices

David J. Palframan, Nam Sung Kim, Mikko H. Lipasti
2012 IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)  
As an alternative that specifically targets random variation, we propose introducing redundancy along the processor datapath in the form of one or more extra bitslices.  ...  This approach allows us to leave dummy slices in the datapath unused to avoid excessively slow critical paths created by delay variations.  ...  As in the case of the ALU, we use Monte Carlo simulations for our analysis of random variation in the register file.  ... 
doi:10.1109/dsn.2012.6263952 dblp:conf/dsn/PalframanKL12 fatcat:x7joiyjsozehdjafhibnunpoce

Binning optimization based on SSTA for transparently-latched circuits

Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
2009 Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09  
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely  ...  First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with  ...  The gSCM for SSTA Let ξ denotes a set of independent random variables of arbitrary distribution which can be obtained after the PCA (Principal Component Analysis) [17] or ICA (Independent Component Analysis  ... 
doi:10.1145/1687399.1687462 dblp:conf/iccad/GongZTZ09 fatcat:i3irexsq2jf6rcoiz6dwm5ziwy

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
The reasons that justify such a radical transition are presented together with directions for solutions.  ...  ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  ASSPs must compete with other ASSPs for defined market niches. As a result, circuit speed and power constraints are higher for ASSPs than ASICs.  ... 
doi:10.1145/589411.589419 dblp:conf/tau/KeutzerO02 fatcat:f2vkixmlpnelffghweyqzgfyli

From blind certainty to informed uncertainty

Kurt Keutzer, Michael Orshansky
2002 Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02  
The reasons that justify such a radical transition are presented together with directions for solutions.  ...  ABSTRACT The accuracy, computational efficiency, and reliability of static timing analysis have made it the workhorse for verifying the timing of synchronous digital integrated circuits for more than a  ...  ASSPs must compete with other ASSPs for defined market niches. As a result, circuit speed and power constraints are higher for ASSPs than ASICs.  ... 
doi:10.1145/589418.589419 fatcat:abyqt4qbmbad7cvervw4v57sma

An Energy-Efficient Current-Starved Inverter Based Strong Physical Unclonable Function with Enhanced Temperature Stability

Yuan Cao, Wenhan Zheng, Xiaojin Zhao, Chip-Hong Chang
2019 IEEE Access  
The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations.  ...  A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter.  ...  In the following subsections, the important figures of merit (FoMs) for evaluating the PUF, including randomness, uniqueness, reliability, power/energy consumption and speed, are measured and analyzed.  ... 
doi:10.1109/access.2019.2932022 fatcat:6dolly2sqzf5jbg7jvhps2pllu

Fast error aware model for arithmetic and logic circuits

Samy Zaynoun, Muhammad S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh
2012 2012 IEEE 30th International Conference on Computer Design (ICCD)  
With operating voltage just under the critical voltage, the propagation delay becomes longer than the original clock period and the original latch fails to correctly sample the data.  ...  With further sub-critical voltage scaling, the supply voltage will be low enough that both latches fail to sample the data correctly. The last situation described is not useful and is undesirable.  ... 
doi:10.1109/iccd.2012.6378659 dblp:conf/iccd/ZaynounKEKK12 fatcat:34jqi77j4fazfjuzrpjrecqyc4
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