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High-speed query processing over high-speed networks

Wolf Rödiger, Tobias Mühlbauer, Alfons Kemper, Thomas Neumann
2015 Proceedings of the VLDB Endowment  
Second, a novel communication multiplexer tailored for analytical database workloads using remote direct memory access (RDMA) and low-latency network scheduling for high-speed communication with almost  ...  Modern database clusters entail two levels of networks: connecting CPUs and NUMA regions inside a single server in the small and multiple servers in the large.  ...  SACK enables fast recovery from packet loss, which is especially relevant for high-speed links.  ... 
doi:10.14778/2856318.2856319 fatcat:aqpagqu5ibc4li5rm65nwh5efu

High-Speed Query Processing over High-Speed Networks [article]

Wolf Roediger, Tobias Muehlbauer, Alfons Kemper, Thomas Neumann
2015 arXiv   pre-print
Second, a novel communication multiplexer tailored for analytical database workloads using remote direct memory access (RDMA) and low-latency network scheduling for high-speed communication with almost  ...  Modern database clusters entail two levels of networks: connecting CPUs and NUMA regions inside a single server in the small and multiple servers in the large.  ...  SACK enables fast recovery from packet loss, which is especially relevant for high-speed links.  ... 
arXiv:1502.07169v4 fatcat:girygakxsfewrp3u6jcyz54oea

Speeding Up FPGA Placement via Partitioning and Multithreading

Cristinel Ababei
2009 International Journal of Reconfigurable Computing  
One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms.  ...  In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997).  ...  Acknowledgments This work was supported by the Electrical and Computer Engineering Department at North Dakota State University.  ... 
doi:10.1155/2009/514754 fatcat:lasgci26r5fvrmikm5czpudare

Area-speed tradeoffs for hierarchical field-programmable gate arrays

Vi Cuong Chan, David M. Lewis
1996 Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96  
Experiments were also performed to determine the effect of timing optimized placements on routing channel requirements.  ...  These experiments demonstrate that HFPGAs can achieve both better area and speed than symmetrical FPGA architectures [2].  ...  Driven Placement Timing Driven Placement Timing Driven Placement w/ DIC Timing Driven Placement Timing Driven Placement w/ Direct Interconnect Non-Timing Driven Placement Non-Timing Driven Placement for  ... 
doi:10.1145/228370.228378 dblp:conf/fpga/ChanL96 fatcat:l6by44fbzvcmfcdf244czwfc5y

Interconnect enhancements for a high-speed PLD architecture

Michael Hutton, Sergey Shumarayev, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate  ...  During the architecture definition phase described in this paper Jay Schleicher lead the software team, and Tony Ngai the IC design team.  ...  ACKNOWLEDGMENTS The authors on this paper were the primary technical contributors to the high-level interconnect design of the Dali architecture but only a small part of the overall IC design, layout and  ... 
doi:10.1145/503049.503050 fatcat:gflllg3imfclvo2mfj6yn7ojpm

Interconnect enhancements for a high-speed PLD architecture

Michael Hutton, Sergey Shumarayev, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate  ...  During the architecture definition phase described in this paper Jay Schleicher lead the software team, and Tony Ngai the IC design team.  ...  ACKNOWLEDGMENTS The authors on this paper were the primary technical contributors to the high-level interconnect design of the Dali architecture but only a small part of the overall IC design, layout and  ... 
doi:10.1145/503048.503050 dblp:conf/fpga/HuttonCKMNPPPSS02 fatcat:r5epgryr3jhw7owa2eyr6gave4

Speeding up multiprocessor machines with reconfigurable optical interconnects

W. Heirman, I. Artundo, L. Desmet, J. Dambre, C. Debaes, H. Thienpont, J. Van Campenhout, Louay A. Eldada, El-Hang Lee
2006 Optoelectronic Integrated Circuits VIII  
Parallel optical interconnection technologies can alleviate this bottleneck by providing fast and high-bandwidth links.  ...  allows for extra connections between distant node pairs that communicate intensely, achieving a high virtual network connectivity by providing only a limited number of physical links at each moment in time  ...  Since the reconfiguration interval will typically be in the order of milliseconds, and the extra link selection should be done in only a fraction of this time, we need a fast heuristic that can quickly  ... 
doi:10.1117/12.644114 fatcat:vvuxa6niqrcdxdlvcyc3x6zxgq

High-Speed Dynamic Start-Stop Pipelines

M. Rajesh Babu, CH Venkata Bhikshapathi, CH Aishwarya, B Ashok, K Sumal, D Thirupathi Rao
2020 International journal of recent advances in engineering & technology  
This paper presents several new pipeline templates that extend existing high-speed approaches for linear dynamic logic pipelines, by providing efficient control structures that can accommodate forks and  ...  Timing analysis and SPICE simulations show that the performance overhead of these extensions is fairly low (5% to 20%).  ...  This timing assumption is referred to as a fast precharge assumption.  ... 
doi:10.46564/ijraet.2020.v08i03.002 fatcat:orxnp75xpjawnnxcds76xt7kbq

Speed checker and reporting system

S. Rakesh, M. VenuGopala Chari, K. Balaji Manohar, Y V N Adithya Goud
2022 International Journal of Health Sciences  
A data-driven method is made used to approximate the speed of the car.  ...  In this project, we find the lorries and also track them in web traffic videos and approximate their speed.  ...  It discovers the most efficient limit which will categorize the pictures as desirable and also negative. Yet definitely, there will be errors or misclassifications.  ... 
doi:10.53730/ijhs.v6ns4.9315 fatcat:zrr6uighqrcyjoth522khpeggy

Predicting the Movement Speeds of Animals in Natural Environments

R. S. Wilson, J. F. Husak, L. G. Halsey, C. J. Clemente
2015 Integrative and Comparative Biology  
Synopsis An animal's movement speed affects all behaviors and underlies the intensity of an activity, the time it takes to complete it, and the probability of successfully completing it, but which factors  ...  Despite the critical importance of an animal's choice of speed (hereafter designated as "speed-choice"), we still lack a framework for understanding and predicting how fast animals should move in nature  ...  They also thank Amanda Niehaus for numerous helpful comments and edits, and we also thank Ray Huey, Simon Lailvaux, and an anonymous reviewer for their numerous insightful comments.  ... 
doi:10.1093/icb/icv106 pmid:26493609 fatcat:kop4mjn3bvdlpmqbrc5ukcqmn4

HotSpot Thermal Floorplan Solver Using Conjugate Gradient to Speed Up

Zhonghua Jiang, Ning Xu
2018 Mobile Information Systems  
The experimental results show that the running time of our incremental iterative conjugate gradient solver is speeded up approximately 11x compared with the LU decomposition method for case ami49, and  ...  We also defined the relative sparse matrix in the iterative thermal floorplan of Simulated Annealing framework algorithm, and the iterative method of relative sparse matrix could be applied to other iterative  ...  It then presented a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and  ... 
doi:10.1155/2018/2921451 fatcat:7yuathojd5db3pdaxemollolbm

High-resolution, high-speed photorefractive incoherent-to-coherent optical converter

P. Bernasconi, G. Montemezzani, M. Wintermantel, I. Biaggio, P. Günter
1999 Optics Letters  
We demonstrate a photorefractive incoherent-to-coherent optical converter driven by ultraviolet light that provides a 35-ms response time and an optical resolution of 124 line pairs͞mm.  ...  Our device has a better optical resolution and conversion rate than optically addressed solid-state spatial light modulators based on the photorefractive effect and multiple quantum wells, and it is also  ...  the largest electro-optic coefficient and thus the largest diffraction efficiency.  ... 
doi:10.1364/ol.24.000199 pmid:18071453 fatcat:kory4uliqvdyzm7aa34tfdd3mu

DFT timing design methodology for at-speed BIST

Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip.  ...  This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme.  ...  ACKNOWLEDGEMENTS Many other people helped our development and evaluations.  ... 
doi:10.1145/1119772.1119942 dblp:conf/aspdac/SatoSTKHN03 fatcat:5sw2dwdokrfjto4blwtc55ztgq

Layout and Radiation Tolerance Issues in High-Speed Links

R. Giordano, A. Aloisio, V. Bocci, M. Capodiferro, V. Izzo, L. Sterpone, M. Violante
2015 IEEE Transactions on Nuclear Science  
High-speed optical links are often used in trigger and data acquisition systems of High Energy Physics (HEP) experiments for data transfer, trigger and fast control distribution.  ...  Moreover, we experimentally verify some custom-developed placement and routing rules aimed at improving the FPGA firmware robustness against configuration upsets.  ...  Cirrone, Francesco Romano and the INFN-LNS staff for their help and support during the proton testing.  ... 
doi:10.1109/tns.2015.2498307 fatcat:abse2af2yjc4fpldu37l2yxbrm

Design and implementation of speed fluctuation reduction for a ball screw feed system at low-speed operation

Zhaoguo Wang, Xianying Feng, Fuxin Du, Hui Li, Zhe Su
2020 Mechanical Sciences  
Compared with the CDFS, the DDFS can suppress the effect of motor torque harmonics on speed fluctuation of the table and improve speed smoothness at low-speed operation.  ...  Then, in the DDFS, we make two motors rotate in the same direction at high speed and differentially synthesize at the ball screw to obtain low-velocity linear motion.  ...  Permanent magnet synchronous motors (PMSMs) are widely used in high-precision servo feed systems since they have high reliability, efficiency, and a torque inertia ratio with a fast dynamic response (  ... 
doi:10.5194/ms-11-163-2020 fatcat:linzuv6itrhgrpmvtofowchmpe
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