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Speculative Versioning Cache

T.N. Vijaykumar, S. Gopal, J.E. Smith, G. Sohi
2001 IEEE Transactions on Parallel and Distributed Systems  
The SVC conceptually unifies cache coherence and speculative versioning by using an organization similar to snooping bus-based coherent caches.  ...  Our proposal, called the Speculative Versioning Cache (SVC), uses distributed caches to eliminate the latency and bandwidth problems of the ARB.  ...  We propose a new solution for speculative versioning called the Speculative Versioning Cache [8] (SVC), for hierarchical execution models.  ... 
doi:10.1109/71.970565 fatcat:4gmlo2zr6nc6dp2owujouudb2i

Speculative versioning cache

S. Gopal, T.N. Vijaykumar, J.E. Smith, G.S. Sohi
Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture  
The SVC conceptually unifies cache coherence and speculative versioning by using an organization similar to snooping bus-based coherent caches.  ...  Our proposal, called the Speculative Versioning Cache (SVC), uses distributed caches to eliminate the latency and bandwidth problems of the ARB.  ...  We propose a new solution for speculative versioning called the Speculative Versioning Cache [8] (SVC), for hierarchical execution models.  ... 
doi:10.1109/hpca.1998.650559 dblp:conf/hpca/GopalVSS98 fatcat:c2l23zhpjfbrdm5yq46so5brou

Prophet: A Speculative Multi-threading Execution Model with Architectural Support Based on CMP

Zhaoyu Dong, Yinliang Zhao, Yuanke Wei, Xuhao Wang, Shaolong Song
2009 2009 International Conference on Scalable Computing and Communications; Eighth International Conference on Embedded Computing  
Prophet multi-versioning Cache system along with thread state control mechanism in architectural support are utilized for buffering the speculative data, and a snooping bus based cache coherence protocol  ...  This paper researches speculative thread-level parallelism of general purpose programs and a speculative multi-threading execution model called Prophet is presented.  ...  All the cache lines generated in speculation have a version greater than 0. We use old bit to denote whether the cache line is with the old version or not.  ... 
doi:10.1109/embeddedcom-scalcom.2009.128 dblp:conf/scalcom/DongZWWS09 fatcat:tx7fhyp2tndjfcrpdpzok6fdcu

Supporting Speculative Multithreading on Simultaneous Multithreaded Processors [chapter]

Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew
2006 Lecture Notes in Computer Science  
In our architecture, the associativity in the cache is used to buffer speculative values.  ...  In this paper we present a novel cache-based architecture support for speculative simultaneous multithreading which can efficiently handle larger threads.  ...  It should make sure that there is only one non-speculative version present in L1 cache.  ... 
doi:10.1007/11945918_19 fatcat:dmozrliaijh5pjyxdb7jgcxxua

Software Logging under Speculative Parallelization [chapter]

María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2004 High Performance Memory Systems  
Speculative parallelization aggressively runs hardto-analyze codes in parallel. Speculative tasks generate unsafe state, which is typically buffered in caches.  ...  Logging also helps to reduce the size of the speculative state to be retained in caches. This paper explores efficient software-only logging for speculative parallelization.  ...  Multiple Local Speculative Versions In some cases, the speculative tasks that share a given cache as a reservoir for their speculative state may try to generate multiple versions of the same variable.  ... 
doi:10.1007/978-1-4419-8987-1_12 fatcat:e6kgtugjvjdqvgjdht5ftoa7ai

Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors

María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2005 ACM Transactions on Architecture and Code Optimization (TACO)  
As speculative tasks run concurrently, they generate unsafe or speculative memory state that needs to be separately buffered and managed in the presence of distributed caches and buffers.  ...  Our key insights are that support for buffering the state of multiple speculative tasks and versions per processor is more complexity-effective than support This paper extends an earlier version that appeared  ...  The cache is not designed to hold multiple speculative versions of the same variable. When a task is about to create a second local speculative version of a variable, it stalls.  ... 
doi:10.1145/1089008.1089010 fatcat:ekiblury4nbrximsgoxonogxhq

Loose-Ordering Consistency for persistent memory

Youyou Lu, Jiwu Shu, Long Sun, Onur Mutlu
2014 2014 IEEE 32nd International Conference on Computer Design (ICCD)  
To enable this, our mechanism requires the tracking of committed transaction ID and support for multi-versioning in the CPU cache.  ...  Second, Speculative Persistence relaxes the ordering of writes between transactions by allowing writes to be speculatively written to persistent memory.  ...  Multiple Versions in the CPU Cache. In Speculative Persistence, multiple versions of a data block are maintained in the volatile CPU cache, similarly to the versioning cache [37] .  ... 
doi:10.1109/iccd.2014.6974684 dblp:conf/iccd/LuSSM14 fatcat:3k2j3ggpyvfsxfvwjkunma2a24

Energy-Efficient Thread-Level Speculation

J. Renau, K. Strauss, L. Ceze, Wei Liu, S.R. Sarangi, J. Tuck, J. Torrellas
2006 IEEE Micro  
One such alternative is thread-level speculation (TLS) on a chip multiprocessor (CMP).  ...  The "Principles of Thread-Level Speculation" sidebar describes TLS foundations in more detail.  ...  The system buffers the version that the speculative task creates, typically in the processor's cache.  ... 
doi:10.1109/mm.2006.11 fatcat:zd2zg2xfgrenboie4btmi52hhq

CMP Support for Large and Dependent Speculative Threads

Christopher B. Colohan, Anastasia Ailamaki, Gregory Steffan, Todd C. Mowry
2007 IEEE Transactions on Parallel and Distributed Systems  
Thread-level speculation (TLS) has proven to be a promising method of extracting parallelism from both integer and scientific workloads, targeting speculative threads that range in size from hundreds to  ...  To support such large and dependent speculative threads, the hardware must be able to buffer the additional speculative state and must also address the more challenging problem of tolerating the resulting  ...  Approaches proposed since the ARB such as the Speculative Versioning Cache (SVC) and the IACOMA [1] , [16] approach also support speculative versions in a more generic cache hierarchy.  ... 
doi:10.1109/tpds.2007.1081 fatcat:xokctk2quvdzjptsqnrd5acyvu

Improving the Performance and Endurance of Persistent Memory with Loose-Ordering Consistency

Youyou Lu, Jiwu Shu, Long Sun, Onur Mutlu
2018 IEEE Transactions on Parallel and Distributed Systems  
To enable this, our mechanism supports the tracking of committed transaction ID and multi-versioning in the CPU cache.  ...  Second, Speculative Persistence relaxes the write ordering between transactions by allowing writes to be speculatively written to persistent memory.  ...  Multiple Versions in the CPU Cache. In Speculative Persistence, multiple versions of a data block are maintained in the volatile CPU cache, similarly to the versioning cache [29].  ... 
doi:10.1109/tpds.2017.2701364 fatcat:6p2yegmf5bamhjhzzhhsbjfd3m

Architectural support for scalable speculative parallelization in shared-memory multiprocessors

Marcelo Cintra, José F. Martínez, Josep Torrellas
2000 Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00  
This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system.  ...  In the table, PRE and SUC stand for predecessor and successor thread respectively, and © and © ¡ refer to two versions of the same word created by the predecessor and successor thread respectively.  ...  with the Speculative Versioning Cache [4] .  ... 
doi:10.1145/339647.363382 fatcat:ymase3zpnfhjbclxdatm3voq7m

Architectural support for scalable speculative parallelization in shared-memory multiprocessors

Marcelo Cintra, José F. Martínez, Josep Torrellas
2000 SIGARCH Computer Architecture News  
This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system.  ...  In the table, PRE and SUC stand for predecessor and successor thread respectively, and © and © ¡ refer to two versions of the same word created by the predecessor and successor thread respectively.  ...  with the Speculative Versioning Cache [4] .  ... 
doi:10.1145/342001.363382 fatcat:akzt3gzhhvabxmq6wqydav3v4i

Multiplex

Chong-Liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
2001 Proceedings of the 15th international conference on Supercomputing - ICS '01  
Our detailed analysis indicates that the dominant overheads in an implicitly-threaded CMP are speculation state overflow due to limited L1 cache capacity, and load imbalance and data dependences in fine-grain  ...  sequential execution stream and speculatively executes them in parallel on multiple processor cores.  ...  A missing load will cause a cache fill from the latest version of the cache block in program order.  ... 
doi:10.1145/377792.377863 dblp:conf/ics/OoiKPEFV01 fatcat:fuke25apgnbn7eqhxod62zsz3m

Ghost loads

Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
2019 Proceedings of the 16th ACM International Conference on Computing Frontiers - CF '19  
., cache updates), caused by the speculatively executed instructions, are commonly left in the system.  ...  The contribution of this work is an evaluation of the cost of hiding speculative side-effects in the cache hierarchy, making them visible only after the speculation has been resolved.  ...  We evaluate two versions of this solution, the Naive and the Eager Non-Speculative (Non-Spec).  ... 
doi:10.1145/3310273.3321558 dblp:conf/cf/SakalisARJKS19 fatcat:i4dmtqu7m5gvxmggbkib2ubi6i

Removing architectural bottlenecks to the scalability of speculative parallelization

Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas
2001 SIGARCH Computer Architecture News  
Speculative thread-level parallelization is a promising way to speed up codes that compilers fail to parallelize.  ...  Consequently, we attempt to identify and eliminate major architectural bottlenecks that limit the scalability of speculative parallelization.  ...  Each level of cache can hold only one version of a given line. However, each cache has a victim cache that can contain multiple versions of the same line.  ... 
doi:10.1145/384285.379264 fatcat:ovbiqt6ayzhsbavke4mcnomdyu
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