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Specifying memory consistency of write buffer multiprocessors

Lisa Higham, Lillanne Jackson, Jalal Kawash
2007 ACM Transactions on Computer Systems  
Write buffering is one of many successful mechanisms that improves the performance and scalability of multiprocessors.  ...  We show that it is not a memory consistency model that corresponds to any implementation on a multiprocessor that uses write-buffers, even though we suspect that the sparc version 9 specification of relaxed  ...  We also thank the Natural Sciences and Engineering Research Council of Canada (NSERC); this research was supported in large part by NSERC grant number OG-POO41900.  ... 
doi:10.1145/1189736.1189737 fatcat:drqm2bxnhfhozoutbthhi2itua

Assessing Programming Costs of Explicit Memory Localization on a Large Scale Shared Memory Multiprocessor

Silvio Picano, Eugene D. Brooks III, Joseph E. Hoag
1992 Scientific Programming  
To make effective use of such an architecture, the programmer is responsible for designing the program's structure to match the underlying multiprocessors capabilities.  ...  We show that an efficient implementation relies heavily on the user's ability to explicitly manage the memory system.  ...  The authors wish to thank Brent Gorda, Tammy W elcome and Linda Woods of the MPCI at LLNL and Ken Sed~ck for their assistance with the parallel programming support for the BBN multiprocessor.  ... 
doi:10.1155/1992/923069 fatcat:cjvqqrdrfvc6nggu7qhhjcrema

Systematic and Automated Multiprocessor System Design, Programming, and Implementation

H. Nikolov, T. Stefanov, E. Deprettere
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The class of multiprocessor platforms we consider is introduced as well.  ...  For modern embedded systems in the realm of highthroughput multimedia, imaging, and signal processing, the complexity of embedded applications has reached a point where the performance requirements of  ...  It has several parameters, such as type, number of I/O ports, speed, etc. 2) Memory Components: Memory components are used to specify the processors' local program and data memories, and to specify the  ... 
doi:10.1109/tcad.2007.911337 fatcat:akppsyu3szgdpg6yp4tb32ra7e

x86-TSO

Peter Sewell, Susmit Sarkar, Scott Owens, Francesco Zappa Nardelli, Magnus O. Myreen
2010 Communications of the ACM  
First, real multiprocessors typically do not provide the sequentially consistent memory that is assumed by most work on semantics and verification.  ...  Instead, they have relaxed memory models, varying in subtle ways between processor families, in which different hardware threads may have only loosely consistent views of a shared memory.  ...  To see why this could be allowed by multiprocessors with FIFO store buffers, suppose that first the Proc 1 write of [y]=2 is buffered, then Proc 0 buffers its write of [x]=1, reads [x]=1 from its own store  ... 
doi:10.1145/1785414.1785443 fatcat:i7av63m3zzhivdof7j6brqc6om

Multi-processor system design with ESPAM

Hristo Nikolov, Todor Stefanov, Ed Deprettere
2006 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis - CODES+ISSS '06  
Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time consuming.  ...  ., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these  ...  Memory components are used to specify the processors' local program and data memories and to specify data communication storages (buffers) between processors.  ... 
doi:10.1145/1176254.1176306 dblp:conf/codes/NikolovSD06 fatcat:qtpcslilh5fwrd55l6jis2xngy

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

R. Rashid, A. Tevanian, M. Young, D. Golub, R. Baron, D. Black, W.J. Bolosky, J. Chew
1988 IEEE transactions on computers  
As of this writing, Mach runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the  ...  Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its  ...  None of the multiprocessors running Mach support TLB consistency.  ... 
doi:10.1109/12.2242 fatcat:5ccs6edc4namtohwne72li5v7a

Formal Reasoning about Hardware and Software Memory Models [chapter]

Abhik Roychoudhury
2002 Lecture Notes in Computer Science  
However, shared memory multiprocessors have a memory model of their own.  ...  The allowed behaviors of any multithreaded Java program on any implementation platform (multi-or uni-processor), are described in terms of a memory consistency model called the Java Memory Model (JMM).  ...  Once the JMM revision is finalized, we plan to perform a full-fledged comparison of the revised JMM with various existing multiprocessor memory models (SPARC TSO, SPARC PSO, DEC Alpha, IBM 370 etc) using  ... 
doi:10.1007/3-540-36103-0_44 fatcat:vk6jcwiq4rhypawfwagfxnoqa4

Memory access buffering in multiprocessors

M. Dubois, C. Scheurich, F. Briggs
1986 SIGARCH Computer Architecture News  
In this paper, we analyze the benefits and problems associated with the buffering of memory requests in shared memory multiprocessors.  ...  Write buffers are often included in a pipelined machine to avoid processor waiting on writes.  ...  SEQUENTIAL CONSISTENCY AND COHERENCE IN MULTIPROCESSORS A simple uniprocessor generally executes instructions one at a time, in the order specified by the program.  ... 
doi:10.1145/17356.17406 fatcat:oavmxceimjdlphbtuxkiyte2pu

Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips

Hristo Nikolov, Todor Stefanov, Ed Deprettere
2007 2007 International Conference on Field Programmable Logic and Applications  
The state-of-the-art development tools support off-chip memory for ( multi-master) shared bus architectures with arbitration of the memory accesses.  ...  The main limitation on the size of an MPSoC that can be built in a single FPGA appears to be the amount of onchip memory.  ...  Because the FIFOs are mapped onto the hierarchical memory system, the memory map of the MPSoC consists of the read and write addresses of their corresponding FIFOx' and FIFOx"' parts.  ... 
doi:10.1109/fpl.2007.4380721 dblp:conf/fpl/NikolovSD07 fatcat:urulvq3nwneblpfmd6jovuyd5m

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

Richard Rashid, Avadis Tevanian, Michael Young, David Golub, Robert Baron
1987 SIGARCH Computer Architecture News  
As of this writing, Maeh runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the  ...  Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its  ...  However, hardware manufacturers do not typically treat the translation lookaside buffer of a memory management unit as another type of cache which also must be kept consistent.  ... 
doi:10.1145/36177.36181 fatcat:xxa2el7u2rbsfjr5qrds5e3kiu

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

Richard Rashid, Avadis Tevanian, Michael Young, David Golub, Robert Baron
1987 SIGPLAN notices  
As of this writing, Maeh runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the  ...  Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its  ...  However, hardware manufacturers do not typically treat the translation lookaside buffer of a memory management unit as another type of cache which also must be kept consistent.  ... 
doi:10.1145/36205.36181 fatcat:2mwa2e46r5cengtwilscj3ujuq

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

Richard Rashid, Avadis Tevanian, Michael Young, David Golub, Robert Baron
1987 ACM SIGOPS Operating Systems Review  
As of this writing, Maeh runs on more than half a dozen uniprocessors and multiprocessors including the VAX family of uniprocessors and multiprocessors, the IBM RT PC, the SUN 3, the Encore MultiMax, the  ...  Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its  ...  However, hardware manufacturers do not typically treat the translation lookaside buffer of a memory management unit as another type of cache which also must be kept consistent.  ... 
doi:10.1145/36204.36181 fatcat:3yomlvnbszadll6kvywvnf7kw4

Boosting the performance of shared memory multiprocessors

P. Stenstrom, M. Brorsson, F. Dahlgren, H. Grahn, M. Dubois
1997 Computer  
An emerging class of shared memory multiprocessors-nonuniform memory access machines with private caches and a cache coherence (CC) protocol-use a directory-based write-invalidate scheme.  ...  S hared memory multiprocessors make it practical to convert sequential programs to parallel ones in a variety of applications.  ...  Boosting the Performance of Shared Memory Multiprocessors S hared memory multiprocessors make it practical to convert sequential programs to parallel ones in a variety of applications.  ... 
doi:10.1109/2.596630 fatcat:igee7gkc2vhk7oyrjstlwzvz3q

Synchronization, coherence, and event ordering in multiprocessors

M. Dubois, C. Scheurich, F.A. Briggs
1988 Computer  
The instruction set of a multiprocessor usually contains basic instructions that are used to implement synchronization and communication between cooperating processes.  ...  The notions of synchronization and communication are difficult to separate because communication  ...  Acknowledgment Through many technical discussions, William Collier of IBM Poughkeepsie helped shape the content of this article.  ... 
doi:10.1109/2.15 fatcat:yflu46ikqjbbdh4tdgalpc5wmm

Shared Memory Multiprocessors [chapter]

2004 Parallel Computing on Heterogeneous Networks  
In a multiprocessor system data can be replicated across multiple locations, including the main memory, private and shared caches, memory write buffers, and processor registers.  ...  A memory consistency model is a broader definition of the memory system behaviour, which specifies ordering constraints imposed on all memory accesses in the system.  ... 
doi:10.1002/0471654167.ch3 fatcat:dvaj7kmetfgr7bkmdrmvzljwda
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