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Analysis of Verification Methodologies Based on a SoC Platform Design

Je-Hoon Lee, Sang-Choon Kim
2011 International Journal of Contents  
We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.  ...  Most complex SoCs need a heterogeneous design development environment for hardware and software co-design.  ...  In virtual prototyping, the whole environment is made by specific kind of software model.  ... 
doi:10.5392/ijoc.2011.7.1.023 fatcat:vn6nefrgergq5d3tjvqtzsgsay

Viable System Verilog Assertions(SVA) Praxis in AMBA AHB-Lite Protocol Design

2020 International Journal of Engineering and Advanced Technology  
Accelerated simulation and emulation using hardware is costly in contrast with software simulation. Prototyping is expedient. Formal verification and intelligent software simulations are frail.  ...  In this design combination of hardware accelerated simulator as a combination of emulator used to accelerate time wheel by using arm amba ahb lite protocol as a design.  ...  Accelerated simulation and emulation using hardware is costly in contrast with software simulation. Prototyping is expedient. Formal verification and intelligent software simulations are frail.  ... 
doi:10.35940/ijeat.e1096.089620 fatcat:zbj3hcrbhzfdneksmheq2svewm

A Formal Object-Oriented Analysis for Software Reliability: Design for Verification [chapter]

Natasha Sharygina, James C. Browne, Robert P. Kurshan
2001 Lecture Notes in Computer Science  
We define and illustrate a set of design rules for OOA models with executable semantics, which lead to automata models with tractable state spaces.  ...  The design rules yield OOA models with functionally structured designs similar to those of hardware systems.  ...  This research was partially supported by the Robotics Research Group of the University of Texas at Austin.  ... 
doi:10.1007/3-540-45314-8_23 fatcat:fj2az7xc5vfopi2wcx6wlhe534

Verification Platform with ARM- and DSP-Based Multiprocessor Architecture for DVB-T Baseband Receivers

Koonshik Cho, June-Young Chang, Han-Jin Cho, Jun-Dong Cho
2008 ETRI Journal  
The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool.  ...  In this paper, we introduce a new verification platform with ARM-and DSP-based multiprocessor architecture.  ...  The platform uses the hardware-software co-design environment of Seamless CVE. Our dual-processor platform verification is divided into hardware and software parts.  ... 
doi:10.4218/etrij.08.0107.0129 fatcat:fghpc7jpdbccfpqcfnsczwsqfe

Proof producing synthesis of arithmetic and cryptographic hardware

Konrad Slind, Scott Owens, Juliano Iyoda, Mike Gordon
2007 Formal Aspects of Computing  
In our talk we'll concentrate on the hardware compiler, but the ARM software compiler and verification projects makes the work relevant to high assurance Systems on a Chip that combine hardware and software  ...  Separate projects are using a verified formal model of the ARM instruction set architecture as a basis for software synthesis and verification.  ...  In our talk we'll concentrate on the hardware compiler, but the ARM software compiler and verification projects makes the work relevant to high assurance Systems on a Chip that combine hardware and software  ... 
doi:10.1007/s00165-007-0028-5 fatcat:gquwxs6cjze73okg5ztvj2775i

Performance verification for ESL design methodology from AADL models

Gaudron Mathieu, Bois Guy, Hugues Jerome, Fellipe Monteiro
2015 2015 International Symposium on Rapid System Prototyping (RSP)  
IRT Workshop Hardware/Software co-development 2015  SpaceStudio API has similarities with AADL one: No  Feedback to the user  ESL design and verification  Emerging electronic design methodology  Focuses  ...  In this work we use SpaceStudio TM 8  Functional/non-functional specification (C/C++/SystemC) IRT Workshop Hardware/Software co-development 2015 FPGA fabric as coprocessors  As the subsystem is part  ... 
doi:10.1109/rsp.2015.7416543 dblp:conf/rsp/MathieuGHM15 fatcat:zbwjbm3udjfrfcrgcaldgkzdrm

Virtual Prototyping Platform for Multiprocessor System-on-Chip Hardware/Software Co-design and Co-verification [chapter]

Arya Wicaksana, Tang Chong Ming
2017 Studies in Computational Intelligence  
This paper describes the implementation of a virtual prototyping platform to address the ever-challenging multiprocessor system-on-chip (MPSoC) hardware/software co-design and co-verification requirements  ...  One approach is to raise the abstraction level of system design and verification to ESL.  ...  Lee Sze Wei, and Mr. Ng Mow Song for the support of this research, for the encouragement, enthusiasm, and immense knowledge. This would not have been possible without their guidance and support.  ... 
doi:10.1007/978-3-319-60170-0_7 fatcat:b652rfjyznhehe4xf3lfrygche

A Comparative Study of Computer-Aided Engineering Techniques for Robot Arm Applications

L. Zouari, S. Chtourou, M. Ben Ayed, S. A. Alshaya
2020 Engineering, Technology & Applied Science Research  
This paper studies different simulation techniques based on Model In the Loop (MIL), Hardware In the Loop (HIL), and Hardware Software In the Loop (HSIL) on a flexible robot arm driven by BDCM in order  ...  Despite the wide use of robotic arms in industries, they still encompass a wide number of complexities.  ...  This approach developed further performers in Ptolemy to integrate it in an HLA and to interface the software in the hardware under verification.  ... 
doi:10.48084/etasr.3885 fatcat:yfdzofkijfbvjmr6eutebovfqq

FPGA-based verification methodology of SoC-type CMOS image signal processor

YounSun Kim, Hong-Sik Kim, Raymond Lee, Sungho Kang
2009 2009 IEEE International SOC Conference (SOCC)  
As a verification method, 4-step verification strategy comprised of ARMcore based platform verification, system verification, algorithm verification and performance verification is used.  ...  To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards -the sensor board, the USB board and the switch board -are used.  ...  Because the ISP hardware and the application software should be adequately revised according to pixel size increase, the ISP integration verification is changed in case of the platform verification, and  ... 
doi:10.1109/soccon.2009.5398051 dblp:conf/socc/KimKLK09 fatcat:25upyihruzgsxpn3fmedslhq5m

Design and Application of a Reconfigurable Embedded System

Ching-Biau Tzeng, Tzuu-Shaang Wey, Li-Dao Fang
2008 2008 Eighth International Conference on Intelligent Systems Design and Applications  
hardware system, programming of drivers, implementation of a real-time operating system and the running of applications, to the final hardware and software testing of the entire system.  ...  This paper documents all relevant knowledge and procedures related to the modeling of a system structure, from the selection of main hardware control components ARM and FPGA, the construction of a workable  ...  for learning hardware/software verification and RTOS programming.  ... 
doi:10.1109/isda.2008.309 dblp:conf/isda/TzengWF08 fatcat:zfkmsv6pdjbvlnbufrsyjlikdy

Hardware/Software Co-Assurance using the Rust Programming Language and ACL2

David Hardin
2022 Electronic Proceedings in Theoretical Computer Science  
By so doing, we leverage a number of existing hardware/software co-assurance tools with a minimum investment of time and effort.  ...  A Rust-based HLS brings a single modern, type-safe, and memory-safe expression language for both hardware and software realizations with high assurance.  ...  of Arm for answering questions about the RAC toolchain; and to Robby and Matthew Weis of Kansas State University for their ongoing work to further our hardware/software co-assurance efforts.  ... 
doi:10.4204/eptcs.359.16 fatcat:2asiptbndfe37h6rp64c6sn7ty

CODESSEAL: Compiler/FPGA Approach to Secure Applications [chapter]

Olga Gelbart, Paul Ott, Bhagirath Narahari, Rahul Simha, Alok Choudhary, Joseph Zambreno
2005 Lecture Notes in Computer Science  
The processor is supplemented with an FPGA-based secure hardware component that is capable of fast encryption and decryption, and performs code integrity verification, authentication, and provides protection  ...  This paper proposes a joint compiler/hardware infrastructure -CODESSEAL -for software protection for fully encrypted execution in which both program and data are in encrypted form in memory.  ...  A number of software and software-hardware tools have been proposed to prevent or detect these kinds of attacks [1, 2, 3, 8] .  ... 
doi:10.1007/11427995_54 fatcat:2kqmjapwdrhibcbjegfcgt4uq4

A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project $$EMC^2$$ [chapter]

Haris Isakovic, Radu Grosu, Denise Ratasich, Jiri Kadlec, Zdenek Pohl, Steve Kerrison, Kyriakos Georgiou, Kerstin Eder, Norbert Druml, Lillian Tadros, Flemming Christensen, Emilie Wheatley (+3 others)
2017 Lecture Notes in Computer Science  
This paper reflects on challenges in scope of hardware architectures and related technologies.  ...  In the sandbox world of cyber-physical systems and internetof-things a number of applications is only eclipsed by a number of products that provide solutions for specific problem or set of problems.  ...  This software runs on a separate ARM core and and utilizes the ToF Co-Processor for hardware-acceleration.  ... 
doi:10.1007/978-3-319-66284-8_12 fatcat:6u7actbbcbgwna37sit2rcuhqq

Instruction-Level Abstraction (ILA)

Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik
2018 ACM Transactions on Design Automation of Electronic Systems  
In contrast to the pre-accelerator era, when the ISA played an important role in verification by enabling a clean separation of concerns between software and hardware, verification of these "accelerator-rich  ...  From the perspective of hardware designers, there is a lack of a common framework for the formal functional specification of accelerator behavior.  ...  Top-down this modeling provides a specification for functional verification of hardware, and bottom-up it provides an abstraction for software/hardware co-verification.  ... 
doi:10.1145/3282444 fatcat:cp5xyfozg5au3l3lyj77xkr2oa

Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems

Pao-Ann Hsiung, Shang-Wei Lin
2008 Computer languages, systems & structures  
software component-based reuse, formal synthesis, and formal verification.  ...  The architecture is also easily extensible because reusable hardware and software design components can be added.  ...  models (an abstract model of other components in the system is used to verify a specific functionally detailed component), transaction-level verification (both hardware and software signals are abstracted  ... 
doi:10.1016/ fatcat:quqshvzry5d2zlkaimtu6biatu
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