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On the Verification of a WiMax Design Using Symbolic Simulation

Salim Ismail Al-Akhras, Sofiène Tahar, Gabriela Nicolescu, Michel Langevin, Pierre Paulin
2013 Electronic Proceedings in Theoretical Computer Science  
We then use symbolic simulation together with equivalence checking and property checking techniques for design verification.  ...  Simulation based techniques have traditionally been used to verify that such model refinements do not change the design functionality.  ...  The performance measurements showed in general that the used symbolic simulation based verification is much more efficient than numerical simulation.  ... 
doi:10.4204/eptcs.122.3 fatcat:5lu7oucvrra3tn3bgzuyoxvh3m

Towards a verification technique for large synchronous circuits [chapter]

Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan
1993 Lecture Notes in Computer Science  
A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient  ...  This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification.  ...  One of the main observations is that the parametric Boolean expressions can be used in variety of ways for efficient symbolic simulation based verification of large synchronous circuits.  ... 
doi:10.1007/3-540-56496-9_10 fatcat:mgmiuxnuhbdadnztml3bsfq2pq

A Survey of Hybrid Techniques for Functional Verification

Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
2007 IEEE Design & Test of Computers  
with symbolic techniques for efficient state space search.  ...  However, there are some differences. First, SIVA uses ATPG and symbolic image computation, whereas Ketchum uses symbolic simulation and SAT-based BMC.  ... 
doi:10.1109/mdt.2007.30 fatcat:ojmxdheqenekzor2ybvtf7z3hi

Verifying next generation electronic systems

Rolf Drechsler, Daniel Grose
2017 2017 International Conference on Infocom Technologies and Unmanned Systems (Trends and Future Directions) (ICTUS)  
Of course, for systems of the latter areas a thorough verification is required. However, due to increasing complexity, verification is still the major bottleneck. Hence, new approaches are required.  ...  In this paper the state-of-theart on verification is reported. Furthermore, recent developments are listed and finally the most pressing challenges for industry and academia are identified. I.  ...  This stateful symbolic simulation approach for SystemC applies symbolic subsumption checking for efficient detection of revisited symbolic states. B.  ... 
doi:10.1109/ictus.2017.8285965 fatcat:ajyzto3v7vhqbnr2xmqakmmzb4

Introductory Paper

Enrico Tronci
2006 International Journal on Software Tools for Technology Transfer (STTT)  
The above situation calls for better and better formal verification techniques at all steps of the design flow.  ...  This special issue is devoted to publishing revised versions of contributions first presented at the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME  ...  Thus, for each of the metrics used in simulation-based verification, it presents a corresponding metric that is suitable for the formal verification setting, and describes an algorithmic way to check it  ... 
doi:10.1007/s10009-005-0212-y fatcat:35xnumzg5vdzxozujfc67w5jgi

Error Diagnosis in Equivalence Checking of High Performance Microprocessors

Alper Sen
2007 Electronical Notes in Theoretical Computer Science  
We use simulation based error diagnosis techniques and present a seamless integration of them in our current verification environments.  ...  We use Symbolic Trajectory based Evalaution (STE) for combinational equivalence checking. STE accurately captures transistor level behaviors.  ...  STE [5] is a powerful verification technique based on symbolic ternary simulation using 0, 1, and unknown value "X".  ... 
doi:10.1016/j.entcs.2006.12.026 fatcat:z6c5ng5jfbgw3ifs62c7cbsee4

Numerical Coverage Estimation for the Symbolic Simulation of Real-Time Systems [chapter]

Farn Wang, Geng-Dian Hwang, Fang Yu
2003 Lecture Notes in Computer Science  
Three numerical coverage metrics for the symbolic simulation of dense-time systems and their estimation methods are presented.  ...  Special techniques to derive numerical estimations of dense-time statespaces have also been developed. Properties of the metrics are also discussed with respect to four criteria.  ...  We believe that our techniques can be used to help future development of various coverage-based verification techniques -including the design of new coverage metrics and coverage-based test-pattern generation  ... 
doi:10.1007/978-3-540-39979-7_11 fatcat:uhqot4caqrfpdjxijhg2r2a5cy

Formal Verification of Designs with Complex Control by Symbolic Simulation [chapter]

Gerd Ritter, Hans Eveking, Holger Hinrichsen
1999 Lecture Notes in Computer Science  
The verification tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification  ...  A new approach for the automatic equivalence checking of behavioral or structural descriptions of designs with complex control is presented.  ...  Acknowledgement The authors would like to thank the anonymous reviewers for helpful comments.  ... 
doi:10.1007/3-540-48153-2_18 fatcat:xikff34jmzcjpc3gwqqvo5azfy

Formal verification of analog and mixed signal designs: A survey

Mohamed H. Zaki, Sofiène Tahar, Guy Bois
2008 Microelectronics Journal  
Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation.  ...  Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time.  ...  In addition to deductive based methods, induction and symbolic based methods were also proposed to prove properties of some classes of AMS designs.  ... 
doi:10.1016/j.mejo.2008.05.013 fatcat:527gyri32nd3vjmnfavyiud36m

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation [chapter]

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
2016 Lecture Notes in Computer Science  
We present the tool ParCoSS for verification of cooperative multithreading programs. Our tool is based on the recently proposed Compiled Symbolic Simulation (CSS) technique.  ...  Additionally, we employ parallelization to further speed-up the verification. The potential of our tool is shown by evaluation.  ...  Introduction In this paper we propose our tool ParCoSS (Parallelized Compiled Symbolic Simulation) for verification of cooperative multithreading programs available in the Extended Intermediate Verification  ... 
doi:10.1007/978-3-319-41540-6_10 fatcat:hjy3tpw34zcpvgal3nc3bweuiu

Enhanced symbolic simulation for efficient verification of embedded array systems

Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited.  ...  The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process.  ...  BACKGROUND Symbolic Trajectory Evaluation (STE) [1] is a formal verification technique that is based on ternary symbolic simulation .  ... 
doi:10.1145/1119772.1119830 dblp:conf/aspdac/FengWCPA03 fatcat:x74rzeza7je3bipgszr4fuagxi

Processor validation: a top-down approach

P. Mishra
2005 IEEE potentials  
Symbolic simulation is an efficient technique that bridges the gap between traditional simulation and full-fledged formal verification.  ...  Design validation techniques fall into two broad categories: simulation-based approaches and formal techniques.  ... 
doi:10.1109/mp.2005.1405799 fatcat:qzai4qh7ajcrpo4x473qyg2lve

Verifying SystemC using an intermediate verification language and symbolic simulation

Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
2013 Proceedings of the 50th Annual Design Automation Conference on - DAC '13  
Furthermore, we propose an efficient symbolic simulator integrating Partial Order Reduction. Experimental comparison with existing approaches has shown its potential.  ...  Formal verification of SystemC is challenging. Before dealing with symbolic inputs and the concurrency semantics, a front-end is required to translate the design to a formal model.  ...  Based on IVL the second contribution of this paper is an efficient symbolic simulator.  ... 
doi:10.1145/2463209.2488877 dblp:conf/dac/LeGHD13 fatcat:ppd3t355mzahrcw6sdkfu6677e

A methodology for validation of microprocessors using symbolic simulation

Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy Abadir
2005 International Journal of Embedded Systems  
The specification is used to generate the necessary reference models for processor validation using symbolic simulation.  ...  ., Krishnamurthy, N. and Abadir, M. (2005) 'A methodology for validation of microprocessors using symbolic simulation', Int.  ...  We would like to acknowledge the members of the ACES laboratory for their inputs.  ... 
doi:10.1504/ijes.2005.008805 fatcat:dhd3uvfm2nbynihv4jtk2arss4

Functional Test Generation Using Constraint Logic Programming [chapter]

Zhihong Zeng, Maciej Ciesielski, Bruno Rouzeyre
2002 IFIP Advances in Information and Communication Technology  
Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation.  ...  This paper presents a novel approach to solving SAT based on Constraint Logic Programming technique.  ...  Symbolic Simulation Given a simulation target, symbolic expressions are generated using symbol propagation techniques.  ... 
doi:10.1007/978-0-387-35597-9_32 fatcat:uhmy4a7uxrgbnj2tq2eaiepclq
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