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Solver-Aided Constant-Time Circuit Verification
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<span title="2021-04-01">2021</span>
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arXiv
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We present Xenon, a solver-aided method for formally verifying that Verilog hardware executes in constant-time. ...
Xenon scales to realistic hardware designs by drastically reducing the effort needed to localize the root cause of verification failures via a new notion of constant-time counterexamples, which Xenon uses ...
Solver Aided Verification: ÒÓÒ's Interactive Loop. Xenon drastically simplifies this time consuming process through a solver-aided workflow that helps finding secrecy assumptions automatically. ...
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SAT-Based Verification Methods and Applications in Hardware Verification
[chapter]
<span title="">2006</span>
<i title="Springer Berlin Heidelberg">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a>
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This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. ...
Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. ...
SAT-Based Applications in Hardware Verification We have implemented our various SAT-based methods in a verification platform called VeriSol (formerly DiVer), targeted at verification of large scale hardware ...
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A Framework for Automated Performance Tuning and Code Verification on GPU Computing Platforms
<span title="">2011</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/t3x4vqewrncrfgn2wu7cafsbsq" style="color: black;">2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum</a>
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In many cases, the development does not realize the full potential of the parallel hardware. ...
We are exploring a code compilation framework that automatically generates and tunes numerical solver codes for optimal performance on graphical processing units. ...
Verification of ODE solvers naturally includes a determination that the solver has solved the equations correctly [2] . ...
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DSVerifier: A Bounded Model Checking Tool for Digital Systems
[chapter]
<span title="">2015</span>
<i title="Springer International Publishing">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a>
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This work presents the Digital-Systems Verifier (DSVerifier), which is a verification tool developed for digital systems. ...
In particular, DSVerifier employs the bounded model checking technique based on satisfiability modulo theories (SMT) solvers, which allows engineers to verify the occurrence of design errors, due to the ...
The mentioned definitions are then fed to the DSVerifier engine, along with hardware specifications and other verification parameters, such as verification time (i.e., maximum time that the verification ...
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A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip
<span title="2018-05-26">2018</span>
<i title="MDPI AG">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a>
</i>
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Other techniques used in the verification flow of hardware systems are Equivalence Checking, Simulation, and Semiformal Verification. ...
We can divide them into two categories: simulation, which needs extremely large amounts of time, and formal verification, which needs unrealistic amounts of resources. ...
increase its complexity and to make hardware formal verification prohibitive most times. ...
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Boosting Verification by Automatic Tuning of Decision Procedures
<span title="">2007</span>
<i title="IEEE">
Formal Methods in Computer Aided Design (FMCAD'07)
</i>
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Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. ...
The resulting, automaticallyderived parameter settings yielded runtimes on average 4.5 times faster on bounded model checking instances and 500 times faster on software verification problems than extensive ...
It also propagates all constants. ...
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Boosting Verification by Automatic Tuning of Decision Procedures
<span title="">2007</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/m7zbvrubpncrdirtdbkz3zch4m" style="color: black;">Formal Methods in Computer Aided Design (FMCAD'07)</a>
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Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. ...
The resulting, automaticallyderived parameter settings yielded runtimes on average 4.5 times faster on bounded model checking instances and 500 times faster on software verification problems than extensive ...
It also propagates all constants. ...
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The JKind Model Checker
[article]
<span title="2018-04-18">2018</span>
<i >
arXiv
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<span class="release-stage" >pre-print</span>
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<span title="2017-12-04">2017</span>
<span class="release-stage" >pre-print</span>
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Smoothing is very important in this context as test cases need to be run on the actual hardware where timing is not precisely controllable. ...
If the model is slightly changed, it is often the case that most of the invariants can be re-proved, leading to reduced verification times. ...
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Growing solver-aided languages with rosette
<span title="">2013</span>
<i title="ACM Press">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/6y3m32grtnfktkp2oo6oqjbvta" style="color: black;">Proceedings of the 2013 ACM international symposium on New ideas, new paradigms, and reflections on programming & software - Onward! '13</a>
</i>
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This paper introduces ROSETTE, a framework for designing solver-aided languages. ...
Our framework frees designers from having to compile their languages to constraints: new languages, and their solver-aided constructs, are defined by shallow (library-based) or deep (interpreterbased) ...
(apply impl bits) (apply spec bits))
14 (error "verification failed on" bits)))) Because TCL is not solver aided, it misses several desirable features. ...
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The JKind Model Checker
[chapter]
<span title="">2018</span>
<i title="Springer International Publishing">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a>
</i>
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Smoothing is very important in this context as test
cases need to be run on the actual hardware where timing is not precisely
controllable. ...
If the model is slightly changed, it is often the case that most of the invariants can be re-proved, leading to reduced verification times. ...
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Evaluation of Cardinality Constraints on SMT-Based Debugging
<span title="">2009</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/je7g4kpl6jbpxdooxmljnhyubm" style="color: black;">2009 39th International Symposium on Multiple-Valued Logic</a>
</i>
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For formal verification of hardware Satisfiability Modulo Theory (SMT) solvers are increasingly applied. ...
The experimental evaluation on debugging instances that contain cardinality constraints shows the strong influence of the encoding on the resulting run-times. ...
The application of SMT solvers to formal hardware verification problems already showed promising results [25] . ...
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Deductive Verification Method of Real-Time Safety Properties for Embedded Assembly Programs
<span title="2019-10-14">2019</span>
<i title="MDPI AG">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a>
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We propose a deductive verification method to verify real-time safety properties, based on discrete time, as follows: (1) First, we construct a timed computational model including the execution time from ...
We can specify real-time properties by RTLTL. By our proposed methods, we are able to achieve verification of the real-time safety properties of an embedded program. ...
We verified whether a timed computational model satisfies RTLTL (Real-Time Linear Temporal Logic) formulas by deductive verification. 3. ...
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Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models
<span title="">2017</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/53qmpjy5rrg7tpgq4h5i5oioju" style="color: black;">2017 25th International Conference on Systems Engineering (ICSEng)</a>
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The iii verification problem is first defined using the state space equations for the given circuit and applying Satisfiability Modulo Theories (SMT) solver to determine a region that encloses complete ...
In this thesis, we present a technique for analog and mixed-signal verification targeting DC verification using Berkeley Short-channel Igfet Models (BSIM) for approximation. ...
The exhaustiveness of underlying search algorithm of SAT solvers has proven to be their greatest asset for digital hardware verification. ...
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A lightweight symbolic virtual machine for solver-aided host languages
<span title="2014-06-05">2014</span>
<i title="Association for Computing Machinery (ACM)">
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Solver-aided domain-specific languages (SDSLs) are an emerging class of computer-aided programming systems. ...
They ease the construction of programs by using satisfiability solvers to automate tasks such as verification, debugging, synthesis, and non-deterministic execution. ...
a single fresh symbolic constant of type expr, and binds the identifier id to that constant every time the form is evaluated. ...
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A lightweight symbolic virtual machine for solver-aided host languages
<span title="">2013</span>
<i title="ACM Press">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/jpubwsjaozha5itdes6pzyz2fm" style="color: black;">Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI '14</a>
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Solver-aided domain-specific languages (SDSLs) are an emerging class of computer-aided programming systems. ...
They ease the construction of programs by using satisfiability solvers to automate tasks such as verification, debugging, synthesis, and non-deterministic execution. ...
a single fresh symbolic constant of type expr, and binds the identifier id to that constant every time the form is evaluated. ...
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