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Software-Hardware Cooperative Memory Disambiguation

R. Huang, A. Garg, M. Huang
The Twelfth International Symposium on High-Performance Computer Architecture, 2006.  
In this paper, we target the load-store queue, a dynamic memory disambiguation logic that is among the least scalable structures in a modern microprocessor.  ...  We propose to use software assistance to identify load instructions that are guaranteed not to overlap with earlier pending stores and prevent them from competing for the resources in the load-store queue  ...  In this paper, we explore a software-hardware cooperative approach to dynamic memory disambiguation.  ... 
doi:10.1109/hpca.2006.1598133 dblp:conf/hpca/HuangGH06 fatcat:cdavjenw2fcvxkgh6uy3w4bvae

Dynamic memory disambiguation using the memory conflict buffer

David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
1994 Proceedings of the sixth international conference on Architectural support for programming languages and operating systems - ASPLOS-VI  
This paper introduces a simple hardware mechanism, referred to as the memory con ict bu er, which facilitates static code scheduling in the presence of memory store load dependences.  ...  Correct program execution is ensured by the memory con ict bu er and repair code provided by the compiler.  ...  with the Illinois Computer laboratory for Aerospace Systems and Software ICLASS.  ... 
doi:10.1145/195473.195534 dblp:conf/asplos/GallagherCMGH94 fatcat:jvtm3gwm2rfbtefjg76fxzrli4

Dynamic memory disambiguation using the memory conflict buffer

David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
1994 ACM SIGOPS Operating Systems Review  
This paper introduces a simple hardware mechanism, referred to as the memory con ict bu er, which facilitates static code scheduling in the presence of memory store load dependences.  ...  Correct program execution is ensured by the memory con ict bu er and repair code provided by the compiler.  ...  with the Illinois Computer laboratory for Aerospace Systems and Software ICLASS.  ... 
doi:10.1145/381792.195534 fatcat:evc3zb2djfey5mzhxr6eehvrdq

Dynamic memory disambiguation using the memory conflict buffer

David M. Gallagher, William Y. Chen, Scott A. Mahlke, John C. Gyllenhaal, Wen-mei W. Hwu
1994 SIGPLAN notices  
This paper introduces a simple hardware mechanism, referred to as the memory con ict bu er, which facilitates static code scheduling in the presence of memory store load dependences.  ...  Correct program execution is ensured by the memory con ict bu er and repair code provided by the compiler.  ...  with the Illinois Computer laboratory for Aerospace Systems and Software ICLASS.  ... 
doi:10.1145/195470.195534 fatcat:3u7elnarsjbmhb4thgvhe2qrra

Maps

Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal
1999 SIGARCH Computer Architecture News  
Unified memory semantics are implemented jointly by the hardware and the compiler.  ...  Static promotion is performed using equivalence class unification and modulo unrolling; memory dependences are enforced through explicit synchronization and software serial ordering.  ...  They emulate in software the task of cache coherence, one which is traditionally performed by complex hardware.  ... 
doi:10.1145/307338.300980 fatcat:uxh76ia7wranhhhvzr65mal6my

Changing interaction of compiler and architecture

S.V. Adve, D. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith, C.H. Gebotys, M.T. Kandemir, D.J. Lilja, A.N. Choudbary, J.Z. Fang, Pen-Chung Yew
1997 Computer  
W ith recent developments in compilation technology and architectural design, the line between traditional hardware and software roles has become increasingly blurred.  ...  The compiler can now see the processor's inner structure, which lets architects exploit sophisticated program analysis techniques to hide branch and memory access delays, for example.  ...  Cooperation strategies.  ... 
doi:10.1109/2.642815 fatcat:eeeujapt6ja5lfjjzwkfgyfn5i

Hiding cache miss penalty using priority-based execution for embedded processors

Sanghyun Park, Aviral Shrivastava, Yunheung Paek
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors.  ...  The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design.  ...  We call this hardware-software cooperative approach to instruction reordering as priority based execution.  ... 
doi:10.1145/1403375.1403665 fatcat:ubpzukffovbvhcnt2arg5hhy3q

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors

Sanghyun Park, Aviral Shrivastava, Yunheung Paek
2008 2008 Design, Automation and Test in Europe  
This paper proposes a hardware-software cooperative approach, called priority-based execution to hide cache miss penalty for embedded processors.  ...  The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design.  ...  We call this hardware-software cooperative approach to instruction reordering as priority based execution.  ... 
doi:10.1109/date.2008.4484840 dblp:conf/date/ParkSP08 fatcat:y72lxu4ex5ezlc4y6iew5vth6i

The Case for Software Health Management

Ashok N. Srivastava, Johann Schumann
2011 2011 IEEE Fourth International Conference on Space Mission Challenges for Information Technology  
due to software anomalies.  ...  Software Health Management (SWHM) is a new field that is concerned with the development of tools and technologies to enable automated detection, diagnosis, prediction, and mitigation of adverse events  ...  ACKNOWLEDGEMENTS The authors would like to thank Eric Cooper, Paul Miner, and the NASA partners working on software health management.  ... 
doi:10.1109/smc-it.2011.14 fatcat:ekwkojxd4nefbggxzozed5sccu

Program phase detection and exploitation

Chen Ding, S. Dwarkadas, M.C. Huang, Kai Shen, J.B. Carter
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Studies of application behavior reveal the nested repetition of large and small program phases, with significant variation among phases in such characteristics as memory reference patterns, memory and  ...  Software-Hardware Cooperative Memory Disambiguation We have examined several microarchitectural performance bottlenecks, especially for highperformance numerical applications.  ...  Based on these techniques, we have obtained encouraging results on dynamic memory management, co-scheduling on multi-threaded chip multi-processors, and software-hardware cooperative memory disambiguation  ... 
doi:10.1109/ipdps.2006.1639570 dblp:conf/ipps/DingDHSC06 fatcat:3syq4573kfb7xa624wp6tdkhaa

Angle-of-arrival-assisted Relative Interferometric localization using Software Defined Radios

Jonathan Friedman, Anna Davitian, Dustin Torres, Danijela Cabric, Mani Srivastava
2009 MILCOM 2009 - 2009 IEEE Military Communications Conference  
We have developed and implemented a software-defined model in Matlab, and have designed, simulated, and implemented an SDR-ARI transceiver utilizing USRP hardware and gnuRadio software.  ...  While, ARI encoding was initially proposed in prior work, no implementation had been completed and only a pure hardware approach to the receiver was reported.  ...  of USRP [2] hardware and gnuRadio [3] software.  ... 
doi:10.1109/milcom.2009.5379787 fatcat:lkolpbb55nhlrp52wwhdix4lq4

Runtime Observer Pairs and Bayesian Network Reasoners On-board FPGAs: Flight-Certifiable System Health Management for Embedded Systems [chapter]

Johannes Geist, Kristin Y. Rozier, Johann Schumann
2014 Lecture Notes in Computer Science  
We describe an instantiation of our System Health Management (SHM) framework, rt-R2U2, on standard FPGA hardware, which is suitable to be deployed on-board a UAS.  ...  Our independent hardware implementation allows us to monitor the system without interfering with the previouslycertified software.  ...  Figure 5B shows a BN computing block, which is built from several separate hardware units (bus interface, local memory, instruction decoder, ALU, etc.).  ... 
doi:10.1007/978-3-319-11164-3_18 fatcat:piehgceiznaptfbmuxwlbx73o4

SecBus, a Software/Hardware Architecture for Securing External Memories

Jeremie Brunel, Renaud Pacalet, Salaheddine Ouaarab, Guillaume Duc
2014 2014 2nd IEEE International Conference on Mobile Cloud Computing, Services, and Engineering  
SecBus is a combined hardware/software architecture that guarantees these two security properties.  ...  This attack can be performed by probing the memory bus, dumping the content of the memory using a memory analyzer or by exploiting flaws in DMA-capable devices.  ...  The size indicator disambiguates this. All other PSPEs can only be 4kB pages PSPEs because they correspond to non 4MB-aligned memory pages.  ... 
doi:10.1109/mobilecloud.2014.49 dblp:conf/mobilecloud/BrunelPOD14 fatcat:2qg3aok4tffnjdcpd5t5itnnim

Enabling the high level synthesis of data analytics accelerators

Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi
2016 Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16  
We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations.  ...  These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism.  ...  In cooperation with the PC, the HMI also enables to easily support atomic memory operations.  ... 
doi:10.1145/2968456.2976764 dblp:conf/codes/MinutoliCTLF16 fatcat:26witebxqbdmte4z66vcntkmpu

IMPACT

Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
1991 SIGARCH Computer Architecture News  
The performance of multiple-instruction-issue processors can be severely limited by the compiler's ability to generate e cient code for concurrent hardware.  ...  We ran experiments to characterize the following architectural design issues: code scheduling model, instruction issue rate, memory load latency, and function unit resource limitations.  ...  for Aerospace Systems and Software ICLASS, and the O ce of Naval Research under Contract N00014-88-K-0656.  ... 
doi:10.1145/115953.115979 fatcat:vv7frppdhbhv5kao2qi53kd254
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