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Efficient Remote Software Management Method based on Dynamic Address Translation for IoT Software Execution Platform in Wireless Sensor Network

Minwoo Jung, Dae-Young Kim, Seokhoon Kim
2016 Indian Journal of Science and Technology  
space of the instruction memory using a dynamic address translation technique.  ...  Application/Improvements: The proposed technique reduces the energy consumption and the packet delay of an IoT device for executing the remote embedded software, as well as realizes a storage-less sensor  ...  Our study proposes a newly designed remote software management technique for efficient instruction code management; this technique involves the modification of the on-chip software code bus architecture  ... 
doi:10.17485/ijst/2016/v9i24/96068 fatcat:k4it67hur5dilgj2tgwxjahxca

Software-managed address translation

B. Jacob, T. Mudge
Proceedings Third International Symposium on High-Performance Computer Architecture  
In this paper we explore software-managed address translation.  ...  Software-managed translation requires 0.05 CPI.  ...  The design is software-managed address translation, or softvm for short.  ... 
doi:10.1109/hpca.1997.569652 dblp:conf/hpca/JacobM97 fatcat:2lzv2hlqsfebjjxnyf4uu2wwyq

Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor

Michael Gschwind
2008 2008 IEEE International Conference on Computer Design  
We find that hardware managed address translation shows a performance benefit of up to 5x, even for simple workloads, by avoiding the costs of accelerator/CPU communication and supervisor management of  ...  We explore memory address translation architecture choices for DMA-based data sharing. In multiprogramming environments, address translation is commonly used to separate processes.  ...  As address translation management is a supervisor software function, attached execution elements accessing memory using physical addresses have no means to translate these virtual addresses and find their  ... 
doi:10.1109/iccd.2008.4751904 dblp:conf/iccd/Gschwind08 fatcat:k2d3xvnxzbh6xd3l3lybvqaaee

Translation lookaside buffer management

Y. I. Klimiankou
2019 Sistemnyj Analiz i Prikladnaâ Informatika  
TLB is an associative cache of the advanced processors, which reduces the overhead of the virtual to physical address translations.  ...  This paper focuses on the Translation Lookaside Buffer (TLB) management as part of memory management.  ...  system should synchronize hardware and software views of address space layout.  ... 
doi:10.21122/2309-4923-2019-4-20-24 fatcat:hkyr47p3gjemrhvbi3lmlxyome

Uniprocessor virtual memory without TLBs

B. Jacob, T. Mudge
2001 IEEE transactions on computers  
Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation.  ...  Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost  ...  BACKGROUND AND RELATED WORK This paper describes software-managed address-translation.  ... 
doi:10.1109/12.926161 fatcat:ohjmphva3bfgbbxn6xny5szkle

The Cost of Software-Based Memory Management Without Virtual Memory [article]

Drew Zagieboylo, G. Edward Suh, Andrew C. Myers
2020 arXiv   pre-print
In fact, in some cases, performance can even improve when address translation is avoided.  ...  We expect this small overhead to be worth the benefit of reducing the complexity and energy usage of address translation.  ...  [1] propose a "Do-It-Yourself" translation mechanism that allows application software to provide its own address translation function.  ... 
arXiv:2009.06789v1 fatcat:dzm46ryrkrghjhrfkfxw7r63lu

Extending BORPH for shared memory reconfigurable computers

Xun Changqing, Wen Mei, Wu Nan, Zhang Chunyuan, Hayden Kwok-Hay So
2012 22nd International Conference on Field Programmable Logic and Applications (FPL)  
Our experiment shows the overhead of shared memory segments management is acceptable. And with independent virtual memory access, bandwidth of repeated shared memory access is high.  ...  In our system, the program of hardware process is not just hardware design, but the software program running on embedded processor in FPGA.  ...  APIs of software library on NIOS2. AOS getvaddr Translate a virtual address to physical address. Deal with page fault if it occurs.  ... 
doi:10.1109/fpl.2012.6339371 dblp:conf/fpl/XunWWZS12 fatcat:euyiascuv5f6nhrwwmi52b7rlu

Virtual memory window for application-specific reconfigurable coprocessors

M. Vuletic, L. Pozzi, P. Ienne
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We show a significant speedup compared to the software versions, while limited penalty is paid for virtualisation.  ...  Since the virtualisation layer components hide physical details of the system, user designed hardware and software become perfectly portable.  ...  and interfacing hardware (WMU), and (3) the translation manager (VMW manager).  ... 
doi:10.1109/tvlsi.2006.878481 fatcat:u66nglhinza3rmlcgppohxxyfy

Virtual memory window for application-specific reconfigurable coprocessors

Miljan Vuletić, Laura Pozzi, Paolo Ienne
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
We show a significant speedup compared to the software versions, while limited penalty is paid for virtualisation.  ...  Since the virtualisation layer components hide physical details of the system, user designed hardware and software become perfectly portable.  ...  and interfacing hardware (WMU), and (3) the translation manager (VMW manager).  ... 
doi:10.1145/996566.996818 dblp:conf/dac/VuleticPI04 fatcat:uazhshlnhrhyhmsovjuutn4ilm

Methodology for validating Nest Memory Management Unit

Nandhini Rajaiah, Jayakumar Sankarannair, Larry Leitner
2019 EAI Endorsed Transactions on Cloud Systems  
One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memory management unit for all I/O devices.  ...  Core MMU translation is used as the reference model to validate nest MMU.  ...  Background The Memory management unit (MMU) of a processor translates the effective address (EA)/virtual address (VA) to physical address (PA).  ... 
doi:10.4108/eai.15-3-2019.162139 fatcat:wnfxgv3bgnakri3pqcuz2pbcoa

Virtual memory in contemporary microprocessors

B. Jacob, T. Mudge
1998 IEEE Micro  
- Software- Hardware- Software- Software- Hardware- support managed managed managed managed managed managed TLB TLB TLB; inverted TLB TLB TLB/hierarchical page table page table Superpages  ...  MIPS was one of the earliest commercial architectures to offer a software-managed TLB, 5 though the Astronautics Corporation of America holds a patent for a software-managed design. 6 In a software-managed  ... 
doi:10.1109/40.710872 fatcat:bkgn2daaw5ew7gaeb3ofvyfykq

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele
2006 2006 IEEE International Conference on Field Programmable Technology  
The system layer releases software programmer and hardware designer from interfacing burdens and, still, achieves significant speedups over software with only limited overheads.  ...  Virtualmemory-enabled hardware accelerators benefit from all abstractions and services already available to software.  ...  The WMU translates virtual addresses demanded by the accelerator (similarly as the MMU does for user software) to real addresses of the local memory divided into pages.  ... 
doi:10.1109/fpt.2006.270312 dblp:conf/fpt/VuleticICS06 fatcat:twl3d6d7gvaztexhki6arxvxgi

Architectural support for translation table management in large address space machines

Jerry Huck, Jim Hays
1993 SIGARCH Computer Architecture News  
Traditional methoak for managing the page translation tables are inappropriate for large address space architectures.  ...  The Hashed Page Table (HPI'), described here, provides a very fast and space ejicient translation table that reduces ovdwad by splitting TLB management responsibilities between hardware and software.  ...  The instruction set provides management instructions to enable and disable the translations, change translations, and control the protection model that is often associated with the translation  ... 
doi:10.1145/173682.165128 fatcat:uefr5qbmizdyjdy6qabcox45oi

Performance improvement by Software controlled Cache Architecture

ISHAN KUMAR, ASIC Engineer Nvidia Corporation Bangalore (India)
2018 Journal of Computer & Information Technology  
The effectiveness of software-controlled cache after integration is tested in a communication based System on chip.  ...  Software Managed Virtual Caches : When software gets involved in cache-fill and decouple, the translation hardware then the software gets the control of the memory system.  ...  This software-managed cache organization works very efficiently. In embedded systems, address space protection is a future issue.  ... 
doi:10.22147/jucit/090502 fatcat:qhadrfjugnf3paac4n5zvq5zmy

The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework [article]

Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, Onur Mutlu
2020 arXiv   pre-print
While the OS controls which programs have access to which VBs, dedicated hardware in the memory controller manages the physical memory allocation and address translation of the VBs.  ...  VBI decouples access protection from memory allocation and address translation.  ...  framework and to software-based memory management.  ... 
arXiv:2005.09748v1 fatcat:fuzajm73gvgjjj7eerrhiyvkwu
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