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Low-Latency Software Polar Decoders

Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross
2016 Journal of Signal Processing Systems  
applications on modern desktop processors and embedded-platform processors.  ...  In this work, we present low-latency software polar decoders that exploit modern processor capabilities.  ...  ACKNOWLEDGEMENT The authors wish to thank Samuel Gagné of École de technologie supérieure and CMC Microsystems for providing access to the Intel Core i7-4770S processor and NVIDIA Tesla K20c graphical  ... 
doi:10.1007/s11265-016-1157-y fatcat:ozsx2cobevbgtjbiio5qunur3u

Custom Low Power Processor for Polar Decoding

Mathieu Leonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jego, Yvon Savaria
2018 2018 IEEE International Symposium on Circuits and Systems (ISCAS)  
In this paper, as an alternative to general purpose processors, we propose an implementation of an Application Specific Instruction set Processor customized for the Successive Cancellation decoding of  ...  The resulting software decoder achieves throughputs similar to state-of-the-art ARM processor implementations, while reducing the energy consumption by a factor 10.  ...  Comparison with an ARM processor The AFF3CT software [18] allows running an optimized software SC decoder on the A57 processor.  ... 
doi:10.1109/iscas.2018.8351739 dblp:conf/iscas/LeonardonLBLJS18 fatcat:vvgmbmk7sjdpjesb63j35hse5y

Energy consumption analysis of software polar decoders on low power processors

Adrien Cassagne, Olivier Aumage, Camille Leroux, Denis Barthou, Bertrand Le Gal
2016 2016 24th European Signal Processing Conference (EUSIPCO)  
A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems.  ...  A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps.  ...  In this study, we propose to investigate the influence of several parameters on the energy consumption of SC software Polar decoders on embedded processors to demonstrate their effectiveness for future  ... 
doi:10.1109/eusipco.2016.7760327 dblp:conf/eusipco/CassagneALBG16 fatcat:ozz4wpazofftligx4ny6dkbbta

2020 Index IEEE Journal on Emerging and Selected Topics in Circuits and Systems Vol. 10

2020 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
for Polar Codes; JETCAS June 2020 189-203 Xue, C., see Cao, S., JETCAS June 2020 217-230 Siamese Networks for Few-Shot Learning on Edge Embedded Devices.  ...  ., +, JETCAS Dec. 2020 433-443 Decoding Deep Learning-Aided Belief Propagation Decoder for Polar Codes.  ... 
doi:10.1109/jetcas.2020.3043859 fatcat:xuvsy4hh6rdq5hj65t7mw7pefa

Fast List Decoders for Polar Codes

Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross
2016 IEEE Journal on Selected Areas in Communications  
In this paper, we present a new algorithm based on unrolling the decoding tree of the code that improves the speed of list decoding by an order of magnitude when implemented in software.  ...  List decoding involves exploring several decoding paths with SC decoding, and therefore tends to be slower than SC decoding itself, by an order of magnitude in practical implementations.  ...  The base stations, which generally have less stringent energy requirements, can use general purpose processors, including SIMD capable embedded ARM processors, to implement the proposed list-CRC decoding  ... 
doi:10.1109/jsac.2015.2504299 fatcat:ixg6ofpgvrfithvn33a42bhzwu

Adaptive Polar-Space Motion Control for Embedded Omnidirectional Mobile Robots with Parameter Variations and Uncertainties

Hsu-Chih Huang, Ching-Chih Tsai, Shui-Chun Lin
2010 Journal of Intelligent and Robotic Systems  
This proposed polar-space robust adaptive motion controller was implemented into an embedded processor using a field-programmable gate array (FPGA) chip.  ...  robot to track the desired trajectory by using hardware/software co-design technique and SoPC (system-on-a-programmable-chip) technology.  ...  RAM On-chip ROM UART PIO Timer SPI QEP Decoder Digital Filter Clock Divider Nios II Embedded Processor Polar-Space Adaptive Controller / + / D/A Converter / System  ... 
doi:10.1007/s10846-010-9438-3 fatcat:wgbi3s3chzatdez5ib7s6flfry

An FPGA-based centralized visible light beacon network [article]

Duc-Phuc Nguyen, Dinh-Dung Le
2019 arXiv   pre-print
Besides, due to the centralized processing, our system model is considered to be more cost-efficient than the dedicated-processor-based models  ...  Indoor localization systems based on Visible Light Communication (VLC) have shown promising advantages compared with systems based on other wireless technologies.  ...  a low-end embedded processor.  ... 
arXiv:1903.06228v1 fatcat:soebiwmfgnc5jjnlhvix44kuoi

Recursive descriptions of polar codes

Noam Presman, Simon Litsyn
2017 Advances in Mathematics of Communications  
Using such description allows an easy development of these algorithms for arbitrary polarizing kernels.  ...  Hardware architectures for these decoding algorithms are also described in a recursive way, both for Arıkan's standard polar codes and for arbitrary polarizing kernels. 2010 Mathematics Subject Classification  ...  Consequently, in order to build polar code decoder of length N using an embedded decoder of polar code of length N/2 (already having N/4 processors), we use an additional array of N/4 PEs, which is referred  ... 
doi:10.3934/amc.2017001 fatcat:pvx3nvbgd5cpzo4trpgv5dsi6m

Design and Architectures for Signal and Image Processing

Markus Rupp, Ahmet T. Erdogan, Bertrand Granado
2009 EURASIP Journal on Embedded Systems  
This Special Issue of the EURASIP Journal of embedded systems is intended to present innovative methods, tools, design methodologies, and frameworks for algorithm-architecture matching approach in the  ...  design flow including system level design and hardware/software codesign, RTOS, system modeling and rapid prototyping, system synthesis, design verification, and performance analysis and estimation.  ...  As an example, a prototype 2 EURASIP Journal on Embedded Systems for 3GPP long-term evolution (LTE) algorithm on a multicore digital signal processor is built, illustrating both the features and the capabilities  ... 
doi:10.1155/2009/674308 fatcat:l2npgnxwavb3xgmedjdzwklv6y

Toward High-Performance Implementation of 5G SCMA Algorithms

Alireza Ghaffari, Mathieu Leonardon, Adrien Cassagne, Camille Leroux, Yvon Savaria
2019 IEEE Access  
The results show that the throughput of an SCMA decoder can be increased by 3.1 to 21 times when compared to the original MPA on different computing platforms using the suggested improvements.  ...  The effects of forwarding error corrections such as polar, turbo, and LDPC codes, as well as different ways of accessing memory and improving power efficiency of modified MPAs are investigated.  ...  Power consumption and energy used per decoded bit is lower on the ARM platform than on the Intel processors.  ... 
doi:10.1109/access.2019.2891597 fatcat:aqaqk3asurcjle6wixosw3nurq

ASAP 2014 program

2014 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors  
Polar Baseband Receiver for Low-End WLAN 70 Yun-Nan Chang and Ting-Chi Tong. Design of a 2D graphics front-end rendering processor 104 Michael Hall and Roger Chamberlain.  ...  Exploring DMA-assisted Prefetching strategies for Software Caches on Multicore Clusters 16 Majid Jalili and Hamid Sarbazi-Azad.  ... 
doi:10.1109/asap.2014.6868622 fatcat:qhye3xi6yzaoxfngx3ta64t4ku

A real-time multiple antenna element testbed for MIMO algorithm development and assessment

J.W. Wallace, B.D. Jeffs, M.A. Jensen
2004 IEEE Antennas and Propagation Society Symposium, 2004.  
This data is passed through global SDRAM on the VME bus via an interrupt handshake to the embedded PC.  ...  Utility of the system is enhanced by a Concurrent VP CP1/P3x embedded PC in each chassis, housing an Intel Pentium III 1 GHz processor with 256MB RAM, and providing connectivity to standard PC peripherals  ... 
doi:10.1109/aps.2004.1330527 fatcat:7gsofyrlizbh3ar7rsd7mkffna

A Framework for Software-Defined Digital Terrestrial Television (DTTV)

O. Bendov
2006 IEEE transactions on broadcasting  
Commercially viable free DTTV will depend on adoption of new technologies, some already available, that will in turn generate new business models.  ...  The ongoing evolution of software-based receivers will provide the backbone for reliable reception indoors of arbitrarily formatted transmission that will not create new interference to other services.  ...  ACKNOWLEDGEMENT Major elements of the system described in this paper originated in July 2004 while the author worked on the design of the master antenna on the Freedom Tower in New York City.  ... 
doi:10.1109/tbc.2006.879933 fatcat:heytmd4b4nc3rhv5agrrpiuwam

Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor

JaWone A Kennedy, Daniel L Noneaker
2012 EURASIP Journal on Wireless Communications and Networking  
A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism.  ...  Many signal-processing algorithms for communications are well matched to stream-processor architectures, including partially parallel implementations of layered decoding algorithms such as the turbo-decoding  ...  An emerging alternative for computationally demanding digital signal processing is a SIMD-optimized DSP designed for embedded systems, exemplified by the stream processor (or on-chip stream co-processor  ... 
doi:10.1186/1687-1499-2012-141 fatcat:mp6xa5ehrrg2bfrgflxtr4cbie

Software Defined Radio – A High Performance Embedded Challenge [chapter]

Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott Mahlke, Trevor Mudge, Krisztian Flautner
2005 Lecture Notes in Computer Science  
An important goal of the wireless industry is to develop hardware platforms that can support multiple protocols implemented in software (software defined radio) to support seamless end-user service over  ...  An equally important goal is to provide higher and higher data rates.  ...  In addition, we have calculated the maximum performance and energy efficiency of three conventional architectures: a digital signal processor (DSP), an embedded processor, and a general purpose processor  ... 
doi:10.1007/11587514_3 fatcat:y3zzuozqezdnjgb4lnfzz6l2za
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