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Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

Carlos J. G. Aguilera, Cristiano P. Chenet, Tiago R. Balen
2016 Journal of Integrated Circuits and Systems  
This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC).  ...  Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.  ...  ACKNOWLEDGMENT This research is supported in part by Brazilian National Council for Scientific and Technological Development (CNPq), under grant number 56947/2014-0.  ... 
doi:10.29292/jics.v11i3.443 fatcat:wfmmqcd2sfaybchzysa3dcbpba

Integrating safety and multimedia subsystems on a Time-Triggered System-on-a-Chip

Roman Obermaisser, Bernhard Fromel, Christian El Salloum, Bernhard Huber
2008 2008 6th IEEE International Conference on Industrial Informatics  
The Time-Triggered System-on-a-Chip (TTSoC) architecture enables the realization of mixed-criticality systems using SoCs.  ...  The integration of subsystems with different criticality enables massive cost reduction by reducing the overall number of devices and networks (e.g., ECUs in car).  ...  The control subsystem is safety-critical and is thus replicated on three redundant SoCs by using Triple Modular Redundancy (TMR).  ... 
doi:10.1109/indin.2008.4618107 fatcat:xcccioq77fhbxc7pxspm6bpanu

A Railway Safety And Security Concept For Low-Power Mixed-Criticality Systems

Ainara Bilbao, Irune Yarza, Jose Luis Montero, Mikel Azkarate-askasua, Nera Gonzalez
2017 Zenodo  
Mixed-criticality cyber physical system provides great advantages in terms of cost, dependability, scalability and competitiveness.  ...  This paper presents the safety concept of a railway signalling use–case, considering a mixed-criticality object controller which includes a power management approach.  ...  items) B.Architecture Triple Modular Redundancy (TMR) nodes with "Composite fail safety": 1.Each node: compliant item (EN 50128/EN 50129 SIL 4, IEC 61508 SIL4) 2.Each node: independent memories and  ... 
doi:10.5281/zenodo.831373 fatcat:3yjcrtnkz5fkjdkw2kg7jd5jim

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design

Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
2013 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)  
This paper proposes a mixed-grained reconfigurable architecture consisting of fine-grained and coarse-grained fabrics, each of which can be configured for different levels of reliability depending on the  ...  Thanks to the fine-grained fabrics, the architecture can accommodate a state machine, which is indispensable for exploiting C-based behavioral synthesis to trade latency with resource usage through multi-step  ...  For example, if triple modular redundancy (TMR) is adopted, the three-fold memory capacity becomes necessary.  ... 
doi:10.1109/reconfig.2013.6732309 dblp:conf/reconfig/KonouraAMOINWHO13 fatcat:25cbtn5adretxgavz4tolzo65u

A Fault Hypothesis for Integrated Architectures

R. Obermaisser
2006 2006 International Workshop on Intelligent Solutions in Embedded Systems  
This insight is significant for supporting mixed criticality systems, in which software components with different criticality levels are collocated on shared node computers.  ...  Otherwise an elevation of the criticality for all software components to the highest criticality level of a software module in the system would become necessary.  ...  IST-004527 and the European IST project DECOS under project No. IST-511764.  ... 
doi:10.1109/wises.2006.237001 fatcat:qckdoibxarbvdizzcu6jf7gl3i

A Fault Hypothesis for Integrated Architectures

R. Obermaisser, P. Peti
2006 2006 International Workshop on Intelligent Solutions in Embedded Systems  
This insight is significant for supporting mixed criticality systems, in which software components with different criticality levels are collocated on shared node computers.  ...  Otherwise an elevation of the criticality for all software components to the highest criticality level of a software module in the system would become necessary.  ...  IST-004527 and the European IST project DECOS under project No. IST-511764.  ... 
doi:10.1109/wises.2006.329115 dblp:conf/wises/ObermaisserP06 fatcat:saxit5brevagdpd2gkzlhwcjgm

Evaluation of a Network-on-Chip designed to deal with multiple processors in a nanosatellite

Liz Cristine Moreira Coutinho, Marcelo Daniel Berejuck
2020 Revista Brasileira de Computação Aplicada  
Nanosatellites are part of a category of artificial satellites with two essential characteristics: reduced size and low cost of raw material for their construction.  ...  This protection was confirmed by simulations carried out with a software that allows the injection of faults, named ModelSim.  ...  Triple Modular Redundancy -TMR TMR is a passive hardware redundancy, and the redundant elements are used to "mask" the faults.  ... 
doi:10.5335/rbca.v12i2.10120 fatcat:uqmelkcmqvex5muaicby52xeom

Cost-effective safety and fault localization using distributed temporal redundancy

Brett H. Meyer, Benton H. Calhoun, John Lach, Kevin Skadron
2011 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11  
Furthermore, by distributing all redundant tasks across different resources, triple-modular redundancy, and therefore fault localization, can be achieved.  ...  One natural approach we have previous introduced is On-Demand Redundancy (ODR), which allows safety-critical and non-critical tasks, traditionally isolated to limit interference, to execute on shared resources  ...  ACKNOWLEDGEMENTS We would like to thank the anonymous reviewers; their comments and insights have made the paper better.  ... 
doi:10.1145/2038698.2038719 dblp:conf/cases/MeyerCLS11 fatcat:v6sabzywxbgy7es6zsxdtkxib4

Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA

Salman Sadruddin, Arshad Aziz
2013 Chinese Journal of Engineering  
Traditionally, triple modular redundancy (TMR) is used for mitigating Single Event Upsets (SEUs). The drawback of using TMR is that it consumes a lot of hardware resources and requires more power.  ...  A novel and highly efficient design of a software defined radiation tolerant baseband module for a LEO satellite telecommand receiver using FPGA is presented.  ...  Muhammad Kashan Mobeen, of Pakistan Space and Upper Atmosphere Research Commission (SUPARCO), for providing guidance and valuable suggestions during this research work.  ... 
doi:10.1155/2013/453872 fatcat:pjvsvvlghzddvpg3imhbyzyhey

The Role of Mixed Criticality Technology in Industry 4.0

José Simó, Patricia Balbastre, Juan Francisco Blanes, José-Luis Poza-Luján, Ana Guasque
2021 Electronics  
This evolution of industrial systems forces the appearance of new technical requirements for software architectures that enable the consolidation of multiple applications in common hardware platforms—including  ...  The levels and mechanisms of interaction between components are analyzed while considering the impact that the handling of multiple levels of criticality has on the architecture itself—and on the functionalities  ...  In this example, a triple redundancy of critical systems is considered necessary. This redundancy requires the deployment of 11 hardware platforms.  ... 
doi:10.3390/electronics10030226 fatcat:32r6s4u77rglldnkdkstp3grjy

Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Maria Muñoz-Quijada, Samuel Sanchez-Barea, Daniel Vela-Calderon, Hipolito Guzman-Miranda
2018 Electronics  
In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed.  ...  The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.  ...  Xilinx University Program (XUP) for kindly providing the ISE software.  ... 
doi:10.3390/electronics8010024 fatcat:qtypuccw4jdenph322qk5joeai

Safepower Project: Architecture For Safe And Power-Efficient Mixed-Criticality Systems

Maher Fakih, Alina Lenz, Mikel Azkarate-Askasua, Javier Coronel, Alfons Crespo, Simon Davidmann, Juan Carlos Diaz Garcia, Nera González Romero, Kim Grüttner, Sören Schreiner, Razi Seyyedi, Roman Obermaisser (+6 others)
2017 Zenodo  
The EU project SAFEPOWER1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES).  ...  With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip.  ...  Over ethernet, a camera, a gimbal and a wireless LAN connection will be accessible. As a further safety feature, a triple modular redundancy will be implemented for the flight algorithms.  ... 
doi:10.5281/zenodo.1216870 fatcat:46gbqu45lzct5mhsspuqt5i4wm

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Richard McWilliam, Samir Khan, Michael Farnsworth, Colin Bell
2018 Microelectronics and reliability  
This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies.  ...  Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes  ...  Massively-redundant micro-architectures; variant of quad structures. Triple transistor redundancy scheme for minimal area overhead.  ... 
doi:10.1016/j.microrel.2018.04.001 fatcat:bjr3ynhgs5eirdu3yitgnfh3mm

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

Hiroaki KONOURA, Dawood ALNAJJAR, Yukio MITSUYAMA, Hajime SHIMADA, Kazutoshi KOBAYASHI, Hiroyuki KANBARA, Hiroyuki OCHI, Takashi IMAGAWA, Kazutoshi WAKABAYASHI, Masanori HASHIMOTO, Takao ONOYE, Hidetoshi ONODERA
2014 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
This paper proposes a mixed-grained reconfigurable architecture consisting of fine-grained and coarse-grained fabrics, each of which can be configured for different levels of reliability depending on the  ...  Furthermore, the temporal error rate of an example application due to soft errors in the datapath was measured and demonstrated for reliability-aware mapping. key words: reconfigurable architecture, soft  ...  Shinichi Noda for his contribution to Cyber customization and experiments for architecture evaluation.  ... 
doi:10.1587/transfun.e97.a.2518 fatcat:d7vba3hg7rgkzkois7brwh3xsa

Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor

Julio Perez Acle, Matteo Sonza Reorda, Massimo Violante
2011 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)  
In this paper we consider time redundancy, that allows avoiding the high overhead that more traditional approaches like N-modular redundancy introduce, at an affordable cost in terms of application execution-time  ...  Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission-and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance  ...  The most widely used approach is Triple Modular Redundancy (TMR) [3] [4] that mandates to replicate three times the design (only its memory elements in case of Flash-based FPGAs, or the entire design  ... 
doi:10.1109/lascas.2011.5750278 fatcat:lbbvzo6qbvb5neizvjara6vbwe
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