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Software cache coherence for large scale multiprocessors

L.I. Kontothanassis, M.L. Scott
Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture  
Hardware coherence mechanisms for large-scale machines are complex and costly, but existing software mechanisms have not been fast enough to provide a serious alternative.  ...  For the programs in our test suite, the performance advantage of hardware cache coherence is small enough to suggest that software coherence may be more cost e ective.  ...  Acknowledgements Our thanks to Ricardo Bianchini and Jack Veenstra for the long nights of discussions, idea exchanges and suggestions that helped make this paper possible.  ... 
doi:10.1109/hpca.1995.386534 dblp:conf/hpca/KontothanassisS95 fatcat:rk5qkw7zzzbrhdnzasjlxawyqe

Page 3 of Journal of Research and Practice in Information Technology Vol. 21, Issue 1 [page]

1989 Journal of Research and Practice in Information Technology  
For example, almost all large scale multiprocessors cannot use a shared bus for the processor-memory com- munication mechanism because the bus cannot support the required bandwidth.  ...  In this paper we examine existing cache coher- ence software solutions and propose a new type of cache memory which when combined with software directives solves the coherence problem for a large number  ... 

Cache-coherent distributed shared memory: perspectives on its development and future challenges

J. Hennessy, M. Heinrich, A. Gupta
1999 Proceedings of the IEEE  
Hardware-supported distributed shared memory is becoming the dominant approach for building multiprocessors with moderate to large numbers of processors.  ...  scalable cache coherence.  ...  Furthermore, the lack of cache coherence created a schism in the programming approach used for the widespread small-scale, cache-coherent multiprocessors and the programming approach used for large-scale  ... 
doi:10.1109/5.747863 fatcat:koqfmkqdibaylcxfiheb33bwly

Efficient shared memory with minimal hardware support

Leonidas I. Kontothanassis, Michael L. Scott
1995 SIGARCH Computer Architecture News  
To support this claim we have developed the Cashmere family of software coherence protocols for NCC-NUMA (Non-Cache-Coherent, Non-Uniform-Memory Access) systems, and have used execution-driven simulation  ...  We have found that for a large class of applications the performance of NCC-NUMA multiprocessors rivals that of fully hardware-coherent designs, and significantly surpasses the performance realized on  ...  Small-scale, bus-based shared-memory multiprocessors are now ubiquitous, and several large-scale cache-coherent multiprocessors have been designed in recent years.  ... 
doi:10.1145/218864.218870 fatcat:ukmwch45y5gkvlmqfnkunzd6zi

The scalability of multigrain systems

Donald Yeung
1999 Proceedings of the 13th international conference on Supercomputing - ICS '99  
Researchers have recently proposed coupling small-to mediumscale multiprocessors to build large-scale shared memory machines, known as multigrain shared memory systems.  ...  The paper shows that for multigrain systems with 512 processors, high performance can be achieved on four out of our five applications if each multiprocessor node is at least 16-way.  ...  These systems combine fine-grain cache-coherence mechanisms supported in hardware (within a small-scale multiprocessor) and coarse-grain software page-based mechanisms supported in software (between small-scale  ... 
doi:10.1145/305138.305203 dblp:conf/ics/Yeung99 fatcat:eaao3nq4cfbsdmxy5gnrhyqr5u

MGS

Donald Yeung, John Kubiatowicz, Anant Agarwal
1996 SIGARCH Computer Architecture News  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  We call these systems Distributed Scalable Shared-memory Multiprocessors (DSSMPs).  ...  The authors would like to thank Kavita Bala, Fred Chong, Fredrik Dahlgren, Matt Frank, Silvina Hanono,Kirk Johnson,Kathy Knobe, Victor Lee, and Deborah Wallach for providing valuable comments on early  ... 
doi:10.1145/232974.232980 fatcat:lxsfs2y74ndhfjzqnzrzkpga64

MGS

Donald Yeung, John Kubiatowicz, Anant Agarwal
1996 Proceedings of the 23rd annual international symposium on Computer architecture - ISCA '96  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  We call these systems Distributed Scalable Shared-memory Multiprocessors (DSSMPs).  ...  The authors would like to thank Kavita Bala, Fred Chong, Fredrik Dahlgren, Matt Frank, Silvina Hanono,Kirk Johnson,Kathy Knobe, Victor Lee, and Deborah Wallach for providing valuable comments on early  ... 
doi:10.1145/232973.232980 dblp:conf/isca/YeungKA96 fatcat:nprbszfczrhnzosqc2fb3cktom

Assessing Programming Costs of Explicit Memory Localization on a Large Scale Shared Memory Multiprocessor

Silvio Picano, Eugene D. Brooks III, Joseph E. Hoag
1992 Scientific Programming  
cache coherence mechanism.  ...  We present detailed experimental work involving a commercially available large scale shared memory multiple instruction stream-multiple data stream (MIMD) parallel computer having a software controlled  ...  The authors wish to thank Brent Gorda, Tammy W elcome and Linda Woods of the MPCI at LLNL and Ken Sed~ck for their assistance with the parallel programming support for the BBN multiprocessor.  ... 
doi:10.1155/1992/923069 fatcat:cjvqqrdrfvc6nggu7qhhjcrema

Directory-based cache coherence in large-scale multiprocessors

D. Chaiken, C. Fields, K. Kurihara, A. Agarwal
1990 Computer  
Kirk Johnson, who wrote and tr'aced the Speech application, is responsible for the read-only data processing results.  ...  We would also like to thank the rest of the Alewife group for putting up with our interminable trace-driven simulations. The research reported in this article is funded by DARPA cuntract No.  ...  Cache-coherence schemes prevent this problem by June 1990 This article addresses the usefulness of shared-data caches in large-scale multiprocessors, the relative merits of different coherence schemes  ... 
doi:10.1109/2.55500 fatcat:b3ybdsfjbjabrkc66pjvpkjuse

LimitLESS directories

David Chaiken, John Kubiatowicz, Anant Agarwal
1991 ACM SIGOPS Operating Systems Review  
This protocol is supported by Alewife, a large-scale multiprocessor.  ...  Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coherence.  ...  It was extended by Kiyoshi Kurihara to include several other forms of barrier synchronization such as backos and software combining trees, and to incorporate feedback from the cache controller.  ... 
doi:10.1145/106974.106995 fatcat:uu4t7pp3brfephmzo5mvinbqg4

LimitLESS directories

David Chaiken, John Kubiatowicz, Anant Agarwal
1991 SIGPLAN notices  
This protocol is supported by Alewife, a large-scale multiprocessor.  ...  Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coherence.  ...  It was extended by Kiyoshi Kurihara to include several other forms of barrier synchronization such as backos and software combining trees, and to incorporate feedback from the cache controller.  ... 
doi:10.1145/106973.106995 fatcat:4pjbrbobmfd6nm2jw3oqif5r5y

LimitLESS directories

David Chaiken, John Kubiatowicz, Anant Agarwal
1991 SIGARCH Computer Architecture News  
This protocol is supported by Alewife, a large-scale multiprocessor.  ...  Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coherence.  ...  It was extended by Kiyoshi Kurihara to include several other forms of barrier synchronization such as backos and software combining trees, and to incorporate feedback from the cache controller.  ... 
doi:10.1145/106975.106995 fatcat:bom3nqp3yjh7bbzyorbu4wwybu

LimitLESS directories

David Chaiken, John Kubiatowicz, Anant Agarwal
1991 Proceedings of the fourth international conference on Architectural support for programming languages and operating systems - ASPLOS-IV  
This protocol is supported by Alewife, a large-scale multiprocessor.  ...  Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coherence.  ...  It was extended by Kiyoshi Kurihara to include several other forms of barrier synchronization such as backos and software combining trees, and to incorporate feedback from the cache controller.  ... 
doi:10.1145/106972.106995 dblp:conf/asplos/ChaikenKA91 fatcat:5vnvplywkvd4nouuvymanbs27m

Design of a scalable multiprocessor architecture and its simulation

Der-Lin Pean, Chao-Chin Wu, Huey-Ting Chua, Cheng Chen
2001 Journal of Systems and Software  
Our cluster-based multiprocessor architecture also scales more readily than the current general, or cluster-based, multiprocessor environments. Ó  ...  and software mechanisms.  ...  Each cluster node is a small-scale multiprocessor system and multiple clusters form a large-scale system.  ... 
doi:10.1016/s0164-1212(01)00034-6 fatcat:ix6rj2i3grfbfgk3ha23bd4udq

Multigrain shared memory

Donald Yeung, John Kubiatowicz, Anant Agarwal
2000 ACM Transactions on Computer Systems  
This paper explores the coupling of such small-to medium-scale shared memory multiprocessors through software over a local area network to synthesize larger shared memory systems.  ...  The system leverages the e cient support for ne-grain cache-line sharing within multiprocessor nodes as often as possible, and resorts to coarse-grain page-level sharing across nodes only when absolutely  ...  building block for large-scale multiprocessors for two reasons.  ... 
doi:10.1145/350853.350871 fatcat:s32qyjg7wra7jc6iho426iczra
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