Filters








10 Hits in 5.2 sec

SoC-C

Alastair D. Reid, Krisztian Flautner, Edmund Grimley-Evans, Yuan Lin
2008 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems - CASES '08  
The architectures of system-on-chip (SoC) platforms found in high-end consumer devices are getting more and more complex as designers strive to deliver increasingly compute-intensive applications on near-constant  ...  We demonstrate the effectiveness of SoC-C and its compiler with a "software defined radio" example (the PHY layer of a Digital Video Broadcast receiver) achieving a 3.4x speedup on 4 cores.  ...  SoC-C is a set of language extensions that enables programmers to express efficient system-on-chip programs that exploit the parallelism available in the platform, provides programmers with control over  ... 
doi:10.1145/1450095.1450112 dblp:conf/cases/ReidFGL08 fatcat:tb6x4kxeebfxvfbmcp72vawyqe

libEOMP

Cheng Wang, Sunita Chandrasekaran, Barbara Chapman, Jim Holt
2013 Proceedings of the 2013 International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM '13  
In recent years rapid revolution of Multiprocessor Systemon-Chip (MPSoC) poses new challenges for programming such architectures in an efficient manner.  ...  MCA APIs support device-level communication and resource management for multicore embedded systems.  ...  These severely obstruct developing the OpenMP on embedded systems. Consequently, an efficient OpenMP runtime library for multicore embedded systems is highly required.  ... 
doi:10.1145/2442992.2443001 dblp:conf/ppopp/WangCCH13 fatcat:hpivtj2kijb3nfu6zakmzpxjsa

Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing

David Novo, Alejandro Nocua, Florent Bruguier, Abdoulaye Gamatie, Gillies Sassatelli
2018 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)  
Heterogenous multicore architectures are becoming ubiquitous in high-end smartphones. In this paper, we present a study of two modern heterogeneous multicore architectures based on real measurements.  ...  One architecture implements the well-established ARM big.LITTLE 2-cluster approach while the second one takes a leap forward and extends the concept to 3 clusters.  ...  In this paper, we present the evaluation of two single-ISA heterogeneous multicore System-on-Chip (SoC) architectures present in the mobile market.  ... 
doi:10.1109/recosoc.2018.8449376 dblp:conf/recosoc/NovoNBGS18 fatcat:kcmdqiffyja2fgcielnjfw73gy

OpenMDSP: Extending OpenMP to Program Multi-Core DSP

Jiangzhou He, Wenguang Chen, Guangri Chen, Weimin Zheng, Zhizhong Tang, Handong Ye
2011 2011 International Conference on Parallel Architectures and Compilation Techniques  
Comparing with general purpose multi-processors, the multicore DSPs normally have more complex memory hierarchy, such as on-chip core-local memory and non-cache-coherent shared memory.  ...  We implement the compiler and runtime system for Open-MDSP on FreeScale MSC8156. Benchmarking result shows that seven out of nine benchmarks achieve a speedup of more than 5 with 6 threads.  ...  Finally, we would thank Ziang Hu, Qian Tan and Libin Sun for their help on experiments.  ... 
doi:10.1109/pact.2011.60 dblp:conf/IEEEpact/HeCCZTY11 fatcat:4rwjfzd7ofg5receklzmznekvq

Energy Efficient and Fault Tolerant Multicore Wireless Sensor Network: E²MWSN

Hong-Ling Shi, Kun Mean Hou, Hai-Ying Zhou, Xing Liu
2011 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing  
the Multicore SoC 7.2.1.2.2.Different cells(4-bit, 8-bit, 16-bit, 32-bit) Safe Gate Input Switch Safe Gate Input Switch I O O I I O Sensor Control SoC C C Nano Risc  ...  Therefore, for the next generation WSN node, we suggest to implement WSN node based on multicore SoC chip.  ...  stack, but are common for most applications, such as Over-The-Air upgrade (OTA), etc.  Middleware Abstraction Layer provides higher abstraction interface for application development, like node configuration  ... 
doi:10.1109/wicom.2011.6040317 fatcat:b6qehpnmxjd35go7ycy5v5ru5y

Design, Synthesis, and Test of Networks on Chips

P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli
2005 IEEE Design & Test of Computers  
Figure 1 . 1 Network-on-a-chip (NoC) interconnect architectures: Cliché (a), butterfly fat-tree (BFT) topology (b), Octagon MP-SoC (c), irregular application-specific template (d).  ...  (See the "Programming models for NoCs" sidebar on p. 406.)  ... 
doi:10.1109/mdt.2005.108 fatcat:ftg32fzp2jelppgskbqb34ehiy

DeSyRe: On-demand system reliability

I. Sourdis, C. Strydis, A. Armato, C.S. Bouganis, B. Falsafi, G.N. Gaydadjiev, S. Isaza, A. Malek, R. Mariani, D. Pnevmatikatos, D.K. Pradhan, G. Rauwerda (+6 others)
2013 Microprocessors and microsystems  
The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs).  ...  As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance.  ...  The size of the data and instruction memories is configurable at design-time of the multi-core SoC. C.  ... 
doi:10.1016/j.micpro.2013.08.008 fatcat:jg623r4hmngthk652u7qi6ibme

SpaceCloud Cloud Computing and In-Orbit Demonstration

Oskar Flordal, Aris Synodinos, Mattias Herlitz, Henrik Magnusson, David Steenari, Kyra Förster, Michele Castorina, Tom George, Ian Troxel, Simon Reid, Chris Brunskill, Fredrik Bruhn
2021 Zenodo  
using containerized and isolated virtualization either for execution locally or on networked spacecraft.  ...  These requirements are compounded when factoring in the data movements planned for future spacecraft constellation mesh networks, i.e. connected spacecraft infrastructures for on-orbit fleet management  ...  ACKNOWLEDGEMENTS The authors would like to acknowledge the support of the European Space Agency InCubed program office for project "SpaceCloud Framework", ongoing support from the European Space Agency  ... 
doi:10.5281/zenodo.5522871 fatcat:vio7fmyby5hltogkjatfxzdbse

Efficient implementation of resource-constrained cyber-physical systems using multi-core parallelism

Olaf Neugebauer, Technische Universität Dortmund, Technische Universität Dortmund
2018
On the other side of the performance spectrum, the demand for small energy efficient systems exposed by modern IoT applications increased vastly.  ...  Developing efficient software for such resource-constrained multi-core systems is an error-prone, time-consuming and challenging task.  ...  SoC-C [RFG08] targets an efficient design of parallel applications for System-on-a-Chip (SoC) by introducing language extensions for C.  ... 
doi:10.17877/de290r-18927 fatcat:a5qerjncuzeiflcsh6bee5pt3y

Exploiting tightly-coupled cores

Daniel Bates, Apollo-University Of Cambridge Repository, Apollo-University Of Cambridge Repository
2014
As we move steadily through the multicore era, and the number of processing cores on each chip continues to rise, parallel computation becomes increasingly important.  ...  Individual cores can be made very simple and efficient because they do not need to exploit parallelism internally.  ...  It is strongly influenced by SoC-C (System on Chip C) [108] , and includes constructs for pipeline parallelism, fork-join parallelism and data-parallel loops.  ... 
doi:10.17863/cam.16381 fatcat:6wvapjattzflhdjexbdf465fh4