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Impact of design-manufacturing interface on SoC design methodologies

J.-A. Carballo, S.R. Nassif
2004 IEEE Design & Test of Computers  
The figure assumes an ASIC-style design flow for a SoC. As the top part of the figure shows, modern design methodologies can include custom digital, semicustom digital, and analog design subflows.  ...  Figure 4 illustrates how RETs affect design methodologies in this approach.  ... 
doi:10.1109/mdt.2004.13 fatcat:2boowfvhfvbb3go6kxe35m647u

A comprehensive SoC design methodology for nanometer design challenges

R.R. Kumar, R. Bedi, R. Rajagopal, N. Guruprasad, K. Subbarangaiah, T. Abbasi, D.V.R. Murthy, P.K. Prasad, D.R. Gude
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels.  ...  Methodologies which can address capacity issues have also become mandatory with average design sizes crossing 10M gates for sub-nanometer processes.  ...  , and Co-author of a book on Design Methodology title, "It's the methodology, Stupid!"  ... 
doi:10.1109/vlsid.2006.7 dblp:conf/vlsid/KumarBRGSAMPG06 fatcat:gg3e3zqiojcnlect4hswlyntsy

An SoC design methodology using FPGAs and embedded microprocessors

Nobuyuki Ohba, Kohji Takano
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
This paper proposes an SoC design methodology that makes full use of FPGA capabilities.  ...  Using this methodology, we developed an image processor SoC with cryptographic functions, and we verified the design by running real firmware and application programs.  ...  For SoC design, a top-down design approach is commonly used to maintain design consistency from the system level to the net-list level.  ... 
doi:10.1145/996566.996769 dblp:conf/dac/OhbaT04 fatcat:e7is5xsekvcoxkyb7pvnc6lsk4

HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

R.S. Chakraborty, S. Bhunia
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation.  ...  The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design.  ...  INTRODUCTION R EUSE-BASED system-on-chip (SoC) design using hardware intellectual-property (IP) cores has become a pervasive practice in the industry.  ... 
doi:10.1109/tcad.2009.2028166 fatcat:kxzzulxprnb23llviw6yzqyehm

Panel: Future SoC verification methodology: UVM evolution or revolution?

Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process.  ...  The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved.  ...  UVM is for sure a step further from the point view of the universality of the simulation tool, however, it is not for sure a universal approach with respect to the design and verification language.  ... 
doi:10.7873/date.2014.385 dblp:conf/date/DrechslerCFHMSG14 fatcat:ydgn5xjetrhmziuum4qlfzdtpi

Noise management in highly heterogeneous SoC based integrated circuits

Emre Salman
2010 2010 International SoC Design Conference  
Noise coupling is one of the most fundamental issues in the design of highly heterogeneous, robust integrated systems. A two-step noise management methodology is proposed in this paper.  ...  The second step consists of a methodology to significantly mitigate switching noise.  ...  Due to these reasons, asynchronous design methodologies have had limited acceptance in practical applications.  ... 
doi:10.1109/socdc.2010.5682987 fatcat:lqvcqz3k7vhf5l73jic37x52ue

SoC design methodology: a practical approach

A. Jain, A. Saha, J. Rao
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design  
He has organized and presented two hands-on tutorials on "Rapid-prototyping of Digital Designs" and a half day tutorial on "SoC Design Methodology".  ...  This tutorial will discuss a methodology that is based on the successful design of several digital dominated SoCs such as high-speed low-cost communications Processors, VOP and DSL devices, High performance  ...  He has organized and presented two hands-on tutorials on "Rapid-prototyping of Digital Designs" and a half day tutorial on "SoC Design Methodology".  ... 
doi:10.1109/icvd.2005.151 dblp:conf/vlsid/JainSR05 fatcat:dilbailljzdblkne3wmp43ufia

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Yuanbin Guo, Dennis McCain, JosephR Cavallaro, Andres Takach
2006 EURASIP Journal on Embedded Systems  
Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market  ...  This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology.  ...  However, this type of SoC design space exploration is extremely time consuming because of the current trialand-optimize approaches using hand-coded VHDL/Verilog or graphical schematic design tools [12  ... 
doi:10.1186/1687-3963-2006-014952 fatcat:qnhce2epuzdzthuouofqezgjha

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro, Andres Takach
2006 EURASIP Journal on Embedded Systems  
Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market  ...  This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology.  ...  However, this type of SoC design space exploration is extremely time consuming because of the current trialand-optimize approaches using hand-coded VHDL/Verilog or graphical schematic design tools [12  ... 
doi:10.1155/es/2006/14952 fatcat:xz4vbqoaxvc4pgmmcsduqgujpy

An novel methodology for reducing SoC test data volume on FPGA-based testers

P. Bernardi, M. Sonza Reorda
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
This paper proposes a methodology for reducing the test data volume for the application of SoC Low-Cost test procedures.  ...  The method exploits a tester architecture organization suitable for SoCs testing, which includes a programmable device: the usage of this configurable block joined to the analysis of test pattern regularities  ...  The evaluation of the proposed methodology was done on a sample SoC including self-tested processor and memory cores. Low-cost test methodologies considered are: a.  ... 
doi:10.1145/1403375.1403423 fatcat:62cw22krsrf4nirzbbb7lfqqqe

An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods

Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
2008 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation  
Multi-Processor System on-Chip (MPSoC) architectures are currently designed by using a platform-based approach.  ...  In this paper, an efficient DSE methodology is proposed leveraging traditional Design of Experiments (DoE) and Response Surface Modeling (RSM) techniques.  ...  Abstract-Multi-Processor System on-Chip (MPSoC) architectures are currently designed by using a platform-based approach.  ... 
doi:10.1109/icsamos.2008.4664858 dblp:conf/samos/PalermoSZ08 fatcat:ygunzgd5lferhkhiyoljumqfte

Multifrequency TAM design for hierarchical SOCs

Qiang Xu, N. Nicolici
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper describes a new framework for designing test access mechanisms (TAMs) for modular testing of hierarchical SOCs.  ...  The emergence of megacores in hierarchical systemon-a-chip (SOC) presents new challenges to electronic test automation.  ...  Therefore, prior to tackling the hierarchical SOC test problem, we first investigate a more general multifrequency TAM design approach in a flattened SOC framework.  ... 
doi:10.1109/tcad.2005.852440 fatcat:iqpwpyourbdabcp2vfnbv5klkm

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment.  ...  A self-testing approach for non-programmable cores on an SoC has been proposed in [25] .  ... 
doi:10.1145/513918.514010 dblp:conf/dac/KrsticLCCD02 fatcat:wanljgmetzfb7pncwaxcsm3x5e

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns in the functional environment.  ...  A self-testing approach for non-programmable cores on an SoC has been proposed in [25] .  ... 
doi:10.1145/514009.514010 fatcat:2nluc3xsorg2zegsuuliffxv7i

Computation and communication refinement for multiprocessor SoC design

Radu Marculescu, Umit Y. Ogras, Nicholas H. Zamora
2006 ACM Transactions on Design Automation of Electronic Systems  
Consequently, formal and disciplined system-level design methodologies are in great demand for future multiprocessor design.  ...  Continuous advancements in semiconductor technology enable the design of complex systems-onchips (SoCs) composed of tens or hundreds of IP cores.  ...  ACKNOWLEDGMENTS The authors would like to thank all current and previous members of System Level Design Group (SLD) at Carnegie Mellon University.  ... 
doi:10.1145/1142980.1142983 fatcat:mqdulmqw5ngmljor6imi5c3z5i
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