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Slicing from Formal Semantics: Chisel [chapter]

Adrián Riesco, Irina Măriuca Asăvoae, Mihail Asăvoae
2017 Lecture Notes in Computer Science  
We describe Chisel-a tool that synthesizes a program slicer directly from a given algebraic specification of a programming language operational semantics.  ...  This semantics is assumed to be a rewriting logic specification, given in Maude, while the program is a ground term of this specification.  ...  In comparison with these tools, Chisel proposes a static approach to generating slicers for programming languages starting from their formal semantics.  ... 
doi:10.1007/978-3-662-54494-5_21 fatcat:sms2tbosofgbzajwku2xydo24a

Context-Updates Analysis and Refinement in Chisel [article]

Irina Mariuca Asavoae, Mihail Asavoae, Adrian Riesco
2017 arXiv   pre-print
This paper presents the context-updates synthesis component of Chisel--a tool that synthesizes a program slicer directly from a given algebraic specification of a programming language operational semantics  ...  (By context-updates we understand programming language constructs such as goto instructions or function calls.)  ...  Our approach is implemented in Chisel 3 , a Maude tool for generic program slicing [26] .  ... 
arXiv:1709.06897v1 fatcat:3cec6fk5p5gl3mvdfru3bphbte

Using Relational Verification for Program Slicing [chapter]

Bernhard Beckert, Thorsten Bormer, Stephan Gocht, Mihai Herda, Daniel Lentzsch, Mattias Ulbrich
2019 Lecture Notes in Computer Science  
Program slicing is the process of removing statements from a program such that defined aspects of its behavior are retained.  ...  Based on this, we propose a framework for precise and automatic program slicing.  ...  The approach in [28] uses the formal semantics definitions of a language to automatically generate a slicer for programs written in that language.  ... 
doi:10.1007/978-3-030-30446-1_19 fatcat:z7arpnb7pvf35ejwbp672rtzwe

Strudel: A Corpus-Based Semantic Model Based on Properties and Types

Marco Baroni, Brian Murphy, Eduard Barbu, Massimo Poesio
2010 Cognitive Science  
We present here a fully automatic method for extracting a structured and comprehensive set of concept descriptions directly from an English part-of-speech-tagged corpus.  ...  vinegar and, for that matter, bottles."  ...  Acknowledgments We thank Raffaella Bernardi, Katrin Erk, Alessandro Lenci, and the Cognitive Science editor and reviewers for very useful feedback, as well as the developers of the tools and resources  ... 
doi:10.1111/j.1551-6709.2009.01068.x pmid:21564211 fatcat:mrzvpwblmrfu3gncmvce7gok54

On embedding a hardware description language in Isabelle/HOL

Wilayat Khan, David Sanan, Zhe Hou, Liu Yang
2019 Design automation for embedded systems  
Among the main features of VeriFormal include formal semantics of the language, support for mechanical reasoning about designs and compiler and type checking of modules using Isabelle/HOL as well as VeriFormal  ...  In order to define executable hardware description language while at the same time be fit for formal proofs of properties, a hardware description language VeriFormal, embedded in Isabelle/HOL, was created  ...  and formal tools for hardware description language Verilog.  ... 
doi:10.1007/s10617-019-09226-1 fatcat:gyvbq6ijczf4voaqvvqlqylpae

Generating Configurable Hardware from Parallel Patterns

Raghu Prabhakar, David Koeplinger, Kevin J. Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun
2016 Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '16  
We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines.  ...  of the problems faced when generating hardware from imperative languages.  ...  Authors acknowledge additional support from Oracle.  ... 
doi:10.1145/2872362.2872415 dblp:conf/asplos/PrabhakarKBLSKO16 fatcat:kgbcr4dik5ek7njjzzp77hsluy

Generating Configurable Hardware from Parallel Patterns

Raghu Prabhakar, David Koeplinger, Kevin J. Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun
2016 SIGARCH Computer Architecture News  
We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines.  ...  of the problems faced when generating hardware from imperative languages.  ...  Authors acknowledge additional support from Oracle.  ... 
doi:10.1145/2980024.2872415 fatcat:eaedfjmytvauhltwmxgttnzxn4

Generating Configurable Hardware from Parallel Patterns

Raghu Prabhakar, David Koeplinger, Kevin J. Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun
2016 ACM SIGOPS Operating Systems Review  
We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines.  ...  of the problems faced when generating hardware from imperative languages.  ...  Authors acknowledge additional support from Oracle.  ... 
doi:10.1145/2954680.2872415 fatcat:6ro33h2c3bbu7hf2tcj2x4dwx4

Generating Configurable Hardware from Parallel Patterns

Raghu Prabhakar, David Koeplinger, Kevin J. Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun
2016 SIGPLAN notices  
We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines.  ...  of the problems faced when generating hardware from imperative languages.  ...  Authors acknowledge additional support from Oracle.  ... 
doi:10.1145/2954679.2872415 fatcat:kplhjc26grfhle6koxjepe7pnq

Generating Configurable Hardware from Parallel Patterns [article]

Raghu Prabhakar, David Koeplinger, Kevin Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun
2015 arXiv   pre-print
We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and gen- erating metapipelines.  ...  Functional languages with parallel patterns are a better fit for hardware generation because they both provide high-level abstractions to programmers with little experience in hard- ware design and avoid  ...  Bluespec [2] generates hardware from purely functional descriptions based on Haskell. Chisel [4] is an embedded language in Scala for hardware generation.  ... 
arXiv:1511.06968v1 fatcat:y2xzdhaba5gjdiyv6xfu4lxwvq

LLHD: A Multi-level Intermediate Representation for Hardware Description Languages [article]

Fabian Schuiki, Andreas Kurth, Tobias Grosser, Luca Benini
2020 arXiv   pre-print
LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs.  ...  LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools.  ...  FIRRTL's semantics are closely coupled to those of Chisel and focuses mainly on the synthesis portion of the design flow.  ... 
arXiv:2004.03494v1 fatcat:lke4vh4fgncvldmfbztipltvuu

Predictable Accelerator Design with Time-Sensitive Affine Types [article]

Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang
2020 arXiv   pre-print
This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators.  ...  High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs.  ...  The access sh[i] compiles to A[i].Suffix.A second kind of view lets programs create small slices of a larger memory.  ... 
arXiv:2004.04852v2 fatcat:tqhcu2pqorayfhtp65kc7a4oli

Neural Correlates of Verb Argument Structure Processing

Cynthia K. Thompson, Borna Bonakdarpour, Stephen C. Fix, Henrike K. Blumenfeld, Todd B. Parrish, Darren R. Gitelman, M.-Marsel Mesulam
2007 Journal of Cognitive Neuroscience  
These findings are consistent with processing accounts, which suggest that these regions are crucial for semantic integration. & D  ...  Examination of verbs by argument structure revealed activation of the supramarginal and angular gyri, limited to the left hemisphere only when verbs with two obligatory arguments were compared to verbs with a  ...  A pseudorandomized sequence was generated using the OPTSEQ program (http://surfer.nmr.mgh.harvard.edu/optseq).  ... 
doi:10.1162/jocn.2007.19.11.1753 pmid:17958479 pmcid:PMC2253656 fatcat:75n6zomcv5g7lgxwrwuerm7ciy

Verilog HDL and its ancestors and descendants

Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon Davidmann
2020 Proceedings of the ACM on Programming Languages (PACMPL)  
For large-scale digital logic design, previous schematic-based techniques have transformed into textual registertransfer level (RTL) descriptions written in Verilog.  ...  Rule checking tools look for such things as uninitialized variables, like similar tools for programming languages. Property checkers use assumptions to verify assertions formally.  ...  Many other tools emerged from startups as well as the existing EDA vendors, including formal equivalence checkers, timing analysis tools, fault simulators and test pattern generators.  ... 
doi:10.1145/3386337 fatcat:ttezkcr6pzgppbeofpi23vu2wy

A Framework for the Semantics-aware Modelling of Objects

ANDREAS SCALAS
2021
In particular, the system provides tools for the selection and annotation of geometry based on a formalised contextual knowledge; shape analysis methods to derive new knowledge implicitly encoded in the  ...  The evolution of 3D visual content calls for innovative methods for modelling shapes based on their intended usage, function and role in a complex scenario.  ...  Figure A. 1 : 1 The Main window Figure A. 2 : 2 From left to right: File, Edit and View menu • Slice view: provides several shape analysis tools based on the slicing paradigm; these apply to the template  ... 
doi:10.15167/scalas-andreas_phd2021-03-29 fatcat:lfzzkkcjubdadanif64tl5p7cq
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