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Slice-processors

Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
2001 Proceedings of the 15th international conference on Supercomputing - ICS '01  
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism.  ...  Operation-based prefetchers predict the series of operations, or the computation slice that can be used to calculate forthcoming memory references.  ...  Andreas Moshovos is on leave of absence from Northwestern University. This work was supported in part by an NSF CAREER award and by funds from the University of Toronto.  ... 
doi:10.1145/377792.377856 dblp:conf/ics/MoshovosPB01 fatcat:etizvwwumfffhpzk5bfl2y72ji

An associative processor for air traffic control

Kenneth James Thurber
1971 Proceedings of the May 18-20, 1971, spring joint computer conference on - AFIPS '71 (Spring)  
The bit slice (non-distributed) processor speeds are based upon a bipolar RAM implementation and are what can be achieved with current TTL technology.6 The bit slice processor uses the decoder as a mask  ...  For most applications this processor has been found to have an I/O rate 10 times that of a bit slice processor and 72 that of a distributed logic processor.  ... 
doi:10.1145/1478786.1478794 dblp:conf/afips/Thurber71 fatcat:ntrqdyekovdcpc5xowxkbcqqsy

Simulating Large Scale Parallel Applications Using Statistical Models for Sequential Execution Blocks

Gengbin Zheng, Gagan Gupta, Eric Bohm, Isaac Dooley, Laxmikant V. Kale
2010 2010 IEEE 16th International Conference on Parallel and Distributed Systems  
In this paper, we propose an approach based on statistical models to accurately predict the performance of the sequential execution blocks that comprise a parallel application.  ...  Predicting sequential execution blocks of a large scale parallel application is an essential part of accurate prediction of the overall performance of the application.  ...  ACKNOWLEDGMENTS The research component of BigSim has been supported by NSF awards NGS-0103645 and CSR-SMA-0720827, whereas the BigSim deployment for Blue Waters is being funded by NSF via the Blue Waters  ... 
doi:10.1109/icpads.2010.98 dblp:conf/icpads/ZhengGBDK10 fatcat:g74h7gfkyrdfvbduy7itnylybm

DSP Based System for Real time Voice Synthesis Applications Development [article]

Radu Arsinte, Attila Ferencz, Costin Miron
2008 arXiv   pre-print
This paper describes an experimental system designed for development of real time voice synthesis applications.  ...  The system is composed from a DSP coprocessor card, equipped with an TMS320C25 or TMS320C50 chip, voice acquisition module (ADDA2),host computer (IBM-PC compatible), software specific tools.  ...  A typical sequence of application development is 5.Conclusion The development system was used in the real time implementation of speech synthesiser based on the linear prediction method.This application  ... 
arXiv:0803.0197v1 fatcat:bstxedwvnzdzjirmkj7tcmzhba

Synchronous Transfer Architecture (STA) [chapter]

Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis
2004 Lecture Notes in Computer Science  
A special emphasis is placed on the good synthesis of the generated VHDL model.  ...  require local queues for collecting operands and a controller that determines when exactly an operation is to be started.  ...  Many features of general purpose processors have been adopted in the area of DSPs: Texas Instruments [11] based their high-performance DSP platform on a VLIW architecture.  ... 
doi:10.1007/978-3-540-27776-7_36 fatcat:yurbcjrrofdspnnkzt7agujwim

A VLSI Design Strategy for Graphics [article]

AD. Nimmo, P.F. Lister, R.L. Grimsdale
1988 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware - HWWS '04  
In particular. it focuses on the use of Behavioural simulation tools and includes a worked example.  ...  The tools available for ASIC design now offer the features and functionality necessary to permit ideas to be realised in silicon In a relatively short period of lime, This paper introduces work undertaken  ...  A similar approach was taken by Seillac Co., Ltd. for the Seillac-7 Display Station [4] where a mixture of standard microprocessors, bit-slice processors. multiplier circuits and custom VLSI were employed  ... 
doi:10.2312/eggh/eggh88/003-017 fatcat:wgyam5ftfjfolfqetwhj4ktyea

Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread

Hou Rui, Longbing Zhang, Weiwu Hu
2007 Microprocessors and microsystems  
For a set of memory limited benchmarks selected from Olden benchmark, SPEC CPU2000 as well as Stream benchmark, an average speedup of 3.8% is achieved on dual-core CMP when constructing basic Dynamic Prefetching  ...  This scheme belongs to the hardware-generated thread-based prefetching technique and can decouple the performance and correctness to some extent.  ...  This work is supported by National Basic Research Program of China (2005CB321600), and National Natural Science Foundation of China (NSFC) Grant No. 60325205.  ... 
doi:10.1016/j.micpro.2006.09.002 fatcat:t6ns4nfdojfkvdxsiao3qt677e

Future execution: a hardware prefetching technique for chip multiprocessors

I. Ganusov, M. Burtscher
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
On the way to the second core, each instruction's output is replaced by a prediction of the likely output that the n th future instance of this instruction will produce.  ...  Unlike previously proposed thread-based prefetching approaches, our technique does not need any thread spawning points, features an adjustable lookahead distance, does not require complicated analyzers  ...  Examples of this approach include slice-processors [9] and dynamic speculative precomputation [1] .  ... 
doi:10.1109/pact.2005.23 dblp:conf/IEEEpact/GanusovB05 fatcat:345odgmjxzdn5jycjhhuhuezgi

A high-performance operating system for structured concurrent programs

Luc Bläser
2007 Proceedings of the 4th workshop on Programming languages and operating systems - PLOS '07  
With the advent of multi-processor machines, the time has definitively come to use new programming models that offer an improved support of concurrency.  ...  Therefore, we have developed our own new operating system which has been particularly optimized for high-performance execution of such programs.  ...  Notably, the system guarantees time-sliced processor sharing without any help or knowledge of the programmer, i.e. no coop- Table 1 : Maximum number of processes erative multi-task has to be programmed  ... 
doi:10.1145/1376789.1376800 dblp:conf/sosp/Blaser07 fatcat:ldw4symus5cojodd3vr25vqsmi

Future execution

Ilya Ganusov, Martin Burtscher
2006 ACM Transactions on Architecture and Code Optimization (TACO)  
graph, which greatly increases the number of instructions for which an accurate prediction is available.  ...  While existing prediction-based prefetching methods have proved effective for regular applications, prefetching techniques developed for irregular codes typically require complicated hardware that limits  ...  Examples of this approach include slice-processors [Moshovos et al. 2001 ] and dynamic speculative precomputation [Collins et al. 2001 ].  ... 
doi:10.1145/1187976.1187979 fatcat:2kmqbmidmjgufplpc4hnjge6si

WSCLOCK---a simple and effective algorithm for virtual memory management

Richard W. Carr, John L. Hennessy
1981 Proceedings of the eighth symposium on Operating systems principles - SOSP '81  
The new algorithm combines the most useful feature of WS-a natural and efti:ctive load control that prevents thrashing-with the simplicity and efficiency of CLOCK.  ...  Studies are presented to show that the performance of WS and WSCLOCK are equivalent, even if the savings in overhead are ignored.  ...  The model incorporates both an accurate representation of program behavior based on measured program reference strings, and a general, but detailed, model of a virtual memory operating system.  ... 
doi:10.1145/800216.806596 dblp:conf/sosp/CarrH81 fatcat:6byijkcwz5h73fo62c4nyk3ova

WSCLOCK---a simple and effective algorithm for virtual memory management

Richard W. Carr, John L. Hennessy
1981 ACM SIGOPS Operating Systems Review  
The new algorithm combines the most useful feature of WS-a natural and efti:ctive load control that prevents thrashing-with the simplicity and efficiency of CLOCK.  ...  Studies are presented to show that the performance of WS and WSCLOCK are equivalent, even if the savings in overhead are ignored.  ...  The model incorporates both an accurate representation of program behavior based on measured program reference strings, and a general, but detailed, model of a virtual memory operating system.  ... 
doi:10.1145/1067627.806596 fatcat:ogelkpqukrd73iprvv3dxc3no4

Evaluation of performance of parallel processors in a real-time environment

Gregory R. Lloyd, Richard E. Merwin
1973 Proceedings of the June 4-8, 1973, national computer conference and exposition on - AFIPS '73  
A number of mathematical calculations are susceptible to this type of analysis, e.g., operations on matrices and linear arrays of data.  ...  The following presf'nts an analysis of the results of the above studies of the application of associative parallel processors to both the bulk and Kalman filter problems.  ...  The study reports 9 ,lo,1l were prepared under the direction of the Advanced Ballistic ~,1issile Defense Agency, whose cooperation is greatly appreciated."  ... 
doi:10.1145/1499586.1499629 dblp:conf/afips/LloydM73 fatcat:cpvnjlikbzd3zgvcgwyji3bvmi

Real Time Implementation of Speaker Verification System

K. Mohanaprasad, Jeet Kiran Pawani, Vedant Killa, S. Sankarganesh
2015 Indian Journal of Science and Technology  
Verification of speakers is the use of the voice pattern to check the authenticity of the individual.  ...  In this paper the speaker verification system has been implemented on a real time DSP processor TMS3206713 with a new technique is proposed.  ...  Prior or even before to the discovery of individual DSP chips, most applications of DSP were executed or done with the bit slice processors.  ... 
doi:10.17485/ijst/2015/v8i24/80193 fatcat:k3uolyvskjc7hcj4cwxrkemqa4

SpectrumWare

David L. Tennenhouse, Vanu G. Bose
1995 Proceedings of the 1st annual international conference on Mobile computing and networking - MobiCom '95  
Advances in processor and analog-to-digital conversion technology have made it possible to implement virtual radios that directly sample wide bands of the RF  ...  SpectrumWare effort, especially Don Steinbrecher for the helpful discussions and insight, the reviewers for their helpful comments and Bill Stasior and David Wetherall for their contributions and editing of  ...  Human users, time sliced processors and network links are examples of such dynamically multiplexed resources.  ... 
doi:10.1145/215530.215551 dblp:conf/mobicom/TennenhouseB95 fatcat:t52cirmiebbilc5q2od2sztjoq
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