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Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

Ryan Fung, Vaughn Betz, William Chow
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This work presents the first published algorithm to simultaneously optimize both short-and long-path timing constraints in a Field-Programmable Gate Array (FPGA): the Routing Cost Valleys (RCV) algorithm  ...  Even in cases where there are no short-path timing constraints, RCV outperforms a stateof-the-art FPGA router and improves the maximum clock speed of circuits by an average of 3.2% (and up to 24.7%).  ...  Third, RCV simultaneously optimizes to meet both short-path and long-Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations Ryan Fung, Vaughn Betz, Member, IEEE, and  ... 
doi:10.1109/tcad.2008.917585 fatcat:7ldssgjpczbkteyyuq4za7tn6e

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach

Xiaowei Li, Guihai Yan, Jing Ye, Ying Wang
2018 Science China Information Sciences  
Sci China Inf Sci, 2018, 61(11): 112102, https://doi.self-diagnosis, self-repair, or "3S framework" for short.  ...  performance degradation, mitigating the impact of verification blind spots, and improving the chip yield.  ...  using placement and routing constraints while designing FPGA circuits.  ... 
doi:10.1007/s11432-017-9290-4 fatcat:3mwg4l5pyrashe6het5rlsnlue

Logic Synthesis [chapter]

2017 Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology  
., and Chow, W., Slack allocation and routing to improve FPGA timing while repairing short-path violations, IEEE Transactions on CAD, 27:4, pp. 686-697, April 2008. 132.  ...  for critical path delay xing by swapping cells to low threshold voltage, and leakage power minimization by swapping to high threshold voltage for paths with timing slack; manual reroutes to overcome severe  ... 
doi:10.1201/9781315215112-13 fatcat:me52zpnxyfcczh3choo2p4zulm

Simultaneous short-path and long-path timing optimization for FPGAs

R. Fung, V. Betz, W. Chow
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.  
On a set of 100 large circuits, RCV improves both long-path and short-path timing slack significantly vs. an earlier Computer-Aided Design (CAD) system that focuses solely on long-path timing.  ...  RCV is comprised of a new slack allocation algorithm that produces both minimum and maximum delay budgets for each circuit connection, and a new router that strives to meet and, if possible, surpass these  ...  First, it removes the need for designers to manually repair short-path timing constraint violations.  ... 
doi:10.1109/iccad.2004.1382691 dblp:conf/iccad/FungBC04 fatcat:rtwuw7vys5cfddc4v5je2bnkoe

A Survey of Machine Learning for Computer Architecture and Systems [article]

Nan Wu, Yuan Xie
2021 arXiv   pre-print
Now, it is time to reconsider the relationship between ML and systems, and let ML transform the way that computer architecture and systems are designed.  ...  It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models.  ...  of delivery time to minimize total packets delivery time, capable to handle irregular network topologies and keep a higher network load than the conventional shortest path routing.  ... 
arXiv:2102.07952v1 fatcat:vzj776a6abesljetqobakoc3dq

A parallel integer programming approach to global routing

Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
Due to the effective use of Integer Programming techniques and decomposition, GRIP demonstrates tremendous improvement in wirelength, with the same or lower usage of the routing resources, compared to  ...  Despite the limited parallelism in solving the subproblems and the procedure to parallel -connect them, GRIP takes significant time (from many hours to days) to solve the challenging ISPD 2007 and 2008  ...  For example, if a net has long wirelength and negative timing slacks, then buffers can be added to this net to improve its timing.  ... 
doi:10.1145/1837274.1837323 dblp:conf/dac/WuDL10 fatcat:xbloxsbvjvhzdnnto3hcxkafj4

Limitations and challenges of computer-aided design technology for CMOS VLSI

R.E. Bryant, Kwang-Ting Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J.M. Rabaey, A. Sangiovanni-Vincentelli
2001 Proceedings of the IEEE  
For example, there is a need to design correct and testable chips in a very short time frame and for these chips to meet a competitive requirement.  ...  As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important.  ...  ., number of placeable objects, number of signal nets left unrouted after detailed routing, maximum negative slack over all timing paths, etc.  ... 
doi:10.1109/5.915378 fatcat:jocv62sorfbnjp53u7b76j4mdi

Dependable embedded systems

2008 2008 6th IEEE International Conference on Industrial Informatics  
This Series addresses current and future challenges pertaining to embedded hardware, software, specifications and techniques.  ...  Titles in the Series cover a focused set of embedded topics relating to traditional computing devices as well as hightech appliances used in newer, personal devices, and related topics.  ...  Hideharu Amano at Keio University and its partnering institutions. It was a tremendous help to see to possibilities of FDSOI in silicon very early on.  ... 
doi:10.1109/indin.2008.4618103 fatcat:hal6brsgsjg5rlo3u5xil46pxi

Predictive Reliability and Fault Management in Exascale Systems

Ramon Canal, Carles Hernandez, Rafa Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech PiĄtek, Jaume Abella
2020 ACM Computing Surveys  
Time series have been used to predict whether values will violate a threshold [83] . Observation 7.  ...  While some of these approaches may be applicable to conventional data centers, the uniqueness of the HPC infrastructure requires its own analysis and particular solutions -as we will see in short.  ... 
doi:10.1145/3403956 fatcat:77xcpnevmnc5jfpj6ynhwdng3m

ITERATIVE HEURISTICS FOR CMOL HYBRID CMOS/NANODEVICES CELLS MAPPING ITERATIVE HEURISTICS FOR CMOL HYBRID CMOS/NANODEVICES CELLS MAPPING

Abdalrahman Arafeh, Abdalrahman Arafeh
2012 unpublished
Starting with the longest nets and using slack analysis to keep critical paths the same, rerouting is performed around congestion.  ...  T: Computation Time in Seconds. B: Buffers Inserted. T%: Percentage time improvement. Table 5 . 5 T: Computation Time in Seconds. C: Connectivity Violating Connection.  ... 
fatcat:4ttuaargifhunba2shehpoatp4

Logical partitioning of parallel system simulations

Hari Angepat, Austin, The University Of Texas At, Austin, The University Of Texas At, Derek Chiou, Mattan Erez
2019
Simulation has been a fundamental tool to prototype, hypothesize, and evaluate new ideas to continue improving system performance.  ...  The contribution of this work includes the introduction of optimistic partitioned simulation to improve parallelization, and the introduction of warped partitioned simulation for improved flexibility.  ...  Then for large long runs, FPGAs hosted in the cloud may be used to run large-scale simulations with short turnaround times.  ... 
doi:10.26153/tsw/3268 fatcat:wkotdvpeyrahpatsfwcv4aogti

Lifetime-Aware Task Mapping for Embedded Chip Multiprocessors

Adam Hartman
2018
Several system-level techniques, suchas communication architecture design and slack allocation, are capable of mitigating the effects ofwearout faults and improving system lifetime.  ...  Other lifetime improvement techniques seek to augmentsystems in a cost-effective way to mitigate the effects of wearout faults while task mappingdoes not necessarily require additional investment in hardware  ...  Application of the techniques to place and route for FPGAs.  ... 
doi:10.1184/r1/7423301.v1 fatcat:l2qdeawwqbc2lbp5enq5l6aa6a

Design and Evaluation of a Practical, High Performance Crossbar Scheduler

Jonathan Turner
2009
We show that all schedulers in this class are work-conserving and use this to provide insight into the operation of the Approximate LOOFA scheduler and a stronger motivation for its use.  ...  We also introduce a simple, natural lower bound on the performance of crossbar schedulers and use it to show that a previously proposed "stress test" traffic pattern is in fact difficult to schedule well  ...  Such violations tend to get quickly "repaired" by the compare-and-swap operations done by ALOOFA, but they remain violations.  ... 
doi:10.7936/k70g3hcb fatcat:xqk6nvnbarg3ziegxgm3n66zne

Reliable Design of Three-Dimensional Integrated Circuits

Shengcheng Wang
2018
The second contribution of this dissertation is to develop a comprehensive framework for TSV repair in order to enhance yield and improve reliability in 3D ICs.  ...  a great deal of functionality into small form factors, while reducing cost and improving performance.  ...  In other words, the constraints of timing slack should be taken into account during global partitioning in order to avoid the timing violation when re-routing a signal with distant TSV and achieve timing  ... 
doi:10.5445/ir/1000083354 fatcat:644at3ogxja2zlyxhbgbng636e

Performance Variation in Digital Systems:Workload Dependent Modeling and Mitigation [article]

(:Unkn) Unknown, National Technological University Of Athens
2021
Contrariwise, the timing-related issues can involve short-term solutions such as methods to reduce critical path delay and manage deadline constraints and approaches affecting the system's long-term timing  ...  In reality, dynamic power is also the sum of another component P short−circuit which is the result of short-circuit currents when both pMOS and nMOS paths are conducting.  ...  Mean Time Between Failures includes, in fact, MTTF and Mean Time to Repair (MTTR), which refers to the average time required for an error to be repaired from the moment it has been detected.  ... 
doi:10.26240/heal.ntua.21941 fatcat:6i5vt2rk3jaabdxtublpupx43y
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