Filters








15,866 Hits in 2.8 sec

Skew Circuits of Small Width [chapter]

Nikhil Balaji, Andreas Krebs, Nutan Limaye
2015 Lecture Notes in Computer Science  
This also implies that skew circuits of bounded width are equal in power to skew circuits of width 7.  ...  It is well known that branching programs of bounded width have the same power as skew circuit of bounded width. The naive approach converts a BP of width w to a skew circuit of width w 2 .  ...  We prove that width 2 skew circuits of any size cannot compute parity of two bits. We then study the power of width 3 skew circuits.  ... 
doi:10.1007/978-3-319-21398-9_16 fatcat:7c2ydz3e6zbnjnhkv47lcxvrfa

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

Hyein Lee, Seungwhun Paik, Youngsoo Shin
2008 2008 IEEE/ACM International Conference on Computer-Aided Design  
Experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum clock period for many benchmark  ...  The problem of allocating pulse width (out of discrete number of predefined widths) and scheduling clock skew (within prescribed upper bound) is formulated, for the first time, for optimizing pulsed latch-based  ...  Experiments with 65-nm technology demonstrate that small number of various pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield figure of merit of 0.93 on average (1.0 indicates  ... 
doi:10.1109/iccad.2008.4681578 dblp:conf/iccad/LeePS08 fatcat:7bhoplwe6vbnxholqzm2dnoauq

Resource Trade-offs in Syntactically Multilinear Arithmetic Circuits

Maurice Jansen, Meena Mahajan, B. V. Raghavendra Rao
2013 Computational Complexity  
The class of polynomials computable by polynomial size log depth arithmetic circuits (VNC 1 ) is known to be computable by constant width polynomial degree circuits (VsSC 0 ), but whether the converse  ...  We further strengthen this inclusion, by giving a separate construction that provides a width-efficient simulation for constant width syntactically multilinear circuits by constant width syntactically  ...  We thank the anonymous referees of MFCS 2008, CSR 2009, and of this journal for their insightful comments and suggestions for improving the presentation of the paper.  ... 
doi:10.1007/s00037-013-0072-x fatcat:6jg6o6x5k5bkvm6tazo5dtm4fe

Clock distribution scheme using coplanar transmission lines

Victor H. Cordero, Sunil P Khatri
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
The design is aimed to achieve low skew, low power and extreme high frequency global clock situations.  ...  The design is aimed for clock signaling in the Gigahertz range (we are able to achieve clock rates of 8GHz and above). The clock is transported as an oscillatory wave on a pair of conductors.  ...  wiring dimensions and with a small increase of power consumption (<8.5%) while improving the skew.  ... 
doi:10.1145/1403375.1403613 fatcat:j45xqotntnholcblbsm6bbwjqu

Clock Distribution Scheme using Coplanar Transmission Lines

Victor H. Cordero, Sunil P Khatri
2008 2008 Design, Automation and Test in Europe  
The design is aimed to achieve low skew, low power and extreme high frequency global clock situations.  ...  The design is aimed for clock signaling in the Gigahertz range (we are able to achieve clock rates of 8GHz and above). The clock is transported as an oscillatory wave on a pair of conductors.  ...  wiring dimensions and with a small increase of power consumption (<8.5%) while improving the skew.  ... 
doi:10.1109/date.2008.4484809 dblp:conf/date/CorderoK08 fatcat:cuqlhlf5vrbfriwlbnbxc3bhhe

Optimization of power dissipation and skew sensitivity in clock buffer synthesis

Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Lin
1995 Proceedings of the 1995 international symposium on Low power design - ISLPED '95  
Our experimental results show an average of 49% reduction of power dissipation while reducing clock skew by several orders of magnitude.  ...  from the interconnect of the clock tree.  ...  The short circuit power dissipation can be avoided by careful circuit design, and the static dissipation is small compared to the dynamic power dissipation term.  ... 
doi:10.1145/224081.224113 dblp:conf/islped/ChungKCL95 fatcat:daq2nyipbjfydhczpu5i66dkvy

Stochastic optimization approach to transistor sizing for CMOS VLSI circuits

Sharad Mehrotra, Paul Franzon, Wentai Liu
1994 Proceedings of the 31st annual conference on Design automation conference - DAC '94  
Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.  ...  A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits.  ...  In view of these diculties, we present a new approach to transistor sizing in small, high performance circuits. This approach is based on stochastic modeling of the circuit responses of interest.  ... 
doi:10.1145/196244.196265 dblp:conf/dac/MehrotraFL94 fatcat:rdh5wuruxfdwzgxw53fbmbuxga

A hierarchical decomposition methodology for multistage clock circuits

Ellis, Pileggi, Rutenbar
1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97  
of skew, met strict current density constraints, exhibited good delay matching across uniform wire width and device variations, and was completed in under 10 CPU hours.  ...  † This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas.  ...  The output impedance of the repowering buffers used gives an optimal maximum wire width of 0.04um for this design, which is too small to be realized.  ... 
doi:10.1109/iccad.1997.643530 dblp:conf/iccad/EllisPR97 fatcat:b5pbvvttc5edrc5ilcenguyzry

Small Space Analogues of Valiant's Classes and the Limitations of Skew Formulas

Meena Mahajan, B. V. Raghavendra Rao
2011 Computational Complexity  
In the uniform circuit model of computation, the width of a boolean circuit exactly characterizes the "space" complexity of the computed function.  ...  Without the width restriction, md-arithmetic circuits are known to capture all of VP.  ...  Much of this work was done when the second author was at The Institute of Mathematical Sciences, Chennai.  ... 
doi:10.1007/s00037-011-0024-2 fatcat:bnro4engmva25nobjrwr2cxvmq

Small-Space Analogues of Valiant's Classes [chapter]

Meena Mahajan, B. V. Raghavendra Rao
2009 Lecture Notes in Computer Science  
In the uniform circuit model of computation, the width of a boolean circuit exactly characterises the "space" complexity of the computed function.  ...  Further, we show that read-once exponential sums over a restricted class of constant-width arithmetic circuits are within VQP, and this is the largest known such subclass of poly-log-width circuits with  ...  As a consequence of Lemmas 7, 8, we have the following:  ... 
doi:10.1007/978-3-642-03409-1_23 fatcat:4kfukithbrf7nlpmuhec7hd5v4

Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks

Rupak Samanta, Jiang Hu, Peng Li
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Experimental results on benchmark circuits show that our sizing method can reduce clock skew by 45% on average with very small increase on power dissipation.  ...  Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits.  ...  They would also like to thank the reviewers for their valuable comments and identification of the novelty of the proposed work and recognizing the challenges faced in demonstrating the feasibility.  ... 
doi:10.1109/tvlsi.2009.2019088 fatcat:ysakntuvrbbqrfgaqmmi2lla4y

Discrete buffer and wire sizing for link-based non-tree clock networks

Rupak Samanta, Jiang Hu, Peng Li
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
Experimental results on benchmark circuits show that our sizing method can reduce clock skew by 45% on average with very small increase on power dissipation.  ...  Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits.  ...  They would also like to thank the reviewers for their valuable comments and identification of the novelty of the proposed work and recognizing the challenges faced in demonstrating the feasibility.  ... 
doi:10.1145/1353629.1353667 dblp:conf/ispd/SamantaHL08 fatcat:qd7gheivwbgwpdg5ukec7g4qaa

Adapting the mode profile of planar waveguides to single-mode fibers: a novel method

M. K. Smit, A. H. de Vreede
1991 Applied Optics  
A novel method for coupling single-mode fibers to planar optical circuits with small waveguide dimensions is proposed.  ...  Alignment tolerances are comparable to those of fiber-fiber coupling. The low loss potential of the method is experimentally demonstrated for A1 2 0 3 waveguides on silicon substrates.  ...  The authors are with Delft University of Technology, Department of Electrical Engineering, Laboratory for Telecommunication &  ... 
doi:10.1364/ao.30.002941 pmid:20706338 fatcat:y27sefm3ybhdxipevfk6f6issm

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

H. Sathyamurthy, S.S. Sapatnekar, J.P. Fishburn
1998 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In the design of circuits under very tight timing speci cations, the area overhead of gate sizing can be considerable.  ...  The theoretical basis for the procedure is developed, a new algorithm for timing analysis of acyclic pipeline circuits with deliberate skew is presented, and a sensitivity-based optimizer is used to solve  ...  Therefore, if the number of short path violations in the nal circuit is relatively small, Step 2 will perturb the solution by only a small amount, and the above technique will work well for practical circuits  ... 
doi:10.1109/43.681267 fatcat:eig45moyevhk3hehiva5gwkox4

Buffer insertion and sizing under process variations for low power clock distribution

Joe G. Xi, Wayne W. M. Dai
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
Instead of increasing wire widths or lengths to reduce skew which results in increased p ower dissipation, we use a balanced buer insertion scheme to partition a large clock tree into a number of small  ...  Because asymmetric loads and wire width variations in small subtrees induce very small skew, minimal wire widths are used. This results in minimal wiring capacitance and dynamic power dissipation.  ...  The authors would like to thank Qing Zhu for his help in the writing of the manuscript and for providing the test cases as well as the result of WS.  ... 
doi:10.1145/217474.217576 dblp:conf/dac/XiD95 fatcat:iyjqmioywnfgvh3le4yxd3sxqi
« Previous Showing results 1 — 15 out of 15,866 results