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Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review

Rohan C
2022 International Journal for Research in Applied Science and Engineering Technology  
Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented.  ...  On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively  ...  A 32-bit single cycle RISC-V processor FPGA prototype is demonstrated. The paper describes a RISC-V processor IP that uses a 32-bit RV32IMA architecture with a 5-stage pipeline.  ... 
doi:10.22214/ijraset.2022.44654 fatcat:23m67ihlvvenjgwzoigbngpaei

Designing Application-Specific Heterogeneous Architectures from Performance Models

Thanh Cong, Francois Charot
2019 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)  
We also assess the performance of our RISC-V single-core and RISC-V-based heterogeneous architecture models.  ...  These models are implemented on FPGAs to take advantage of their parallelism and speed up the simulation when architecture complexity increases.  ...  ACKNOWLEDGMENTS The authors would like to thank Bluespec for providing us the Bluespec tools and also Intel Labs for giving us access to a cluster of the integrated BDW/FPGAs, within IL's vLab academic  ... 
doi:10.1109/mcsoc.2019.00045 dblp:conf/mcsoc/CongC19 fatcat:nxpx56t2yna7rhpev4qhutu6ei

Open-Source 32-Bit RISC Soft-Core Processors

Rahul R.Balwaik Rahul R.Balwaik
2013 IOSR Journal of VLSI and Signal processing  
A soft-core processor build using a Field-Programmable Gate Array (FPGA)'s general-purpose logic represents an embedded processor commonly used for implementation.  ...  Some real world applications of these soft-core processors are also discussed followed by the comparison of their several features and characteristics.  ...  The OR1200 is a 32-bit scalar RISC with Harvard micro architecture, 5-stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.  ... 
doi:10.9790/4200-0244346 fatcat:egmlpig2wjcybgyn5md2bdmc2m

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

Young-Don Bae, Seong-Il Park, In-Cheol Park
2003 IEEE Journal of Solid-State Circuits  
100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.  ...  The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories.  ...  Fig. 7 shows a conventional FPGA architecture and the proposed CLC architecture.  ... 
doi:10.1109/jssc.2003.817259 fatcat:e3vzixmpvfflpl434a6uwmoujm

Leveraging the Openness and Modularity of RISC-V in Space

Stefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone
2019 Journal of Aerospace Information Systems  
RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications.  ...  This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors.  ...  Acknowledgments This work was supported by the European Space Agency under the NPI Program, Cobham Gaisler AB, and Delft University of Technology.  ... 
doi:10.2514/1.i010735 fatcat:b4ckmbr2uvhvzi57ltesqyiokm

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference [article]

Imad Al Assir, Mohamad El Iskandarani, Hadi Rayan Al Sandid, Mazen A. R. Saghir
2021 arXiv   pre-print
In this paper we present Arrow, a configurable hardware accelerator architecture that implements a subset of the RISC-V v0.9 vector ISA extension aimed at edge machine learning inference.  ...  Our experimental results show that an Arrow co-processor can execute a suite of vector and matrix benchmarks fundamental to machine learning inference 2 - 78x faster than a scalar RISC processor while  ...  The RISC-V instruction-set architecture (ISA), with its rich set of standard extensions and ease of customization, has become the ISA of choice for innovations in domain-specific processor design.  ... 
arXiv:2107.07169v1 fatcat:kuv7f5fgcncbfdbjoecajgllp4

The Soft Core Processors: A Review

J. B. Nade, Dr. R. V. Sarwadnya
Soft-core processors have advantages like reduced cost, flexibility, platform independence and greater immunity to obsolescence over their hard-core counterparts.  ...  Some soft CPUs are open source while others are proprietary; some are of RISC category while others are of CISC type.  ...  It is basically a Digital Signal Processor and has a RISC architecture based on two 24-bit buses and handles 16/24 bits data.  ... 
doi:10.17148/ijireeice.2015.31241 fatcat:tm4gokuzsvd3tppntalqpqecqy

FPGA Implementation of On-Chip Network

N Murali Krishna
2018 DJ Journal of Advances in Electronics and Communication Engineering  
The proposed architecture is implemented on FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language), and the obtained comparison power graph signifies that it consumes less  ...  power when compared to BETA RISC processor.  ...  [9] Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma and Arijit Mondal, Single Cycle RISC-V Micro Architecture Processor and its FPGA Prototype, International  ... 
doi:10.18831/ fatcat:jfgj5g733zbi5mgkfypfzvn6ga


Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini (+1 others)
2020 Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems  
BYOC is an open-source hardware framework that provides a scalable cache coherence system, that includes out-of-the-box support for four different ISAs (RISC-V 32-bit, RISC-V 64-bit, x86, and SPARCv9)  ...  Heterogeneous architectures and heterogeneous-ISA designs are growing areas of computer architecture and system software research.  ...  We settled on connecting the core with its L1 caches but without its coherence engines. This prototype ran single-core RISC-V assembly tests with just a few days of work.  ... 
doi:10.1145/3373376.3378479 dblp:conf/asplos/BalkindLSGCLLNF20 fatcat:o4pjn4bfjjaejbho2wju2lguam

On-board Compressing of Hyperspectral Images using CCSDS 123

Douglas Santos, Cesar Zeferino, Eduardo Bezerra, Luigi Dilillo, Douglas Melo
2020 Anais do Computer on the Beach  
In this work, weevaluate alternatives to integrate a CCSDS 123 compressor withan embedded processor based on RISC-V and ARM-based architectures.  ...  Considering the constraints associatedto satellites, single-purpose processors have been developedto run these algorithms in Systems-on-Chip (SoC).  ...  e Tecnológico (CNPq) -Processes 315287/2018-7 and 436982/2018-8.  ... 
doi:10.14210/cotb.v11n1.p332-336 fatcat:kir3iw6l7zejjbrgyqqyyjklc4

The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes [chapter]

Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
2018 Lecture Notes in Electrical Engineering  
Such architecture scheme fits one of the main target application domain of the RISC-V instruction set.  ...  We present an open-source processing core compliant with RISC-V on the software side and with the popular Pulpino processor platform on the hardware side, while supporting interleaved multi-threading for  ...  All the cores of the family have been synthesized and tested on Xilinx Series 7 FPGA devices; an IC prototype design is in progress.  ... 
doi:10.1007/978-3-319-93082-4_12 fatcat:lxcs4i2fp5ffvm2ecwohxzkaqm

A Survey on RISC-V Security: Hardware and Architecture [article]

Tao Lu
2021 arXiv   pre-print
This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Based on our survey, we predict the future research and development directions of RISC-V security.  ...  Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA).  ...  They prototyped SIMF in an open source scalar ordered RISC-V processor.  ... 
arXiv:2107.04175v1 fatcat:hr6avyprj5dvpav2pvnmfmvg2a

Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch [article]

Blaise Tine, Fares Elsabbagh, Krishna Yalamarthy, Hyesoon Kim
2021 arXiv   pre-print
To demonstrate the feasibility of the minimally extended RISC-V ISA, we implemented the complete software and hardware stacks of Vortex on FPGA.  ...  We argue that one of the reasons for the lack of open-source infrastructure for GPUs is rooted in the complexity of their ISA and software stacks.In this work, we first propose an ISA extension to RISC-V  ...  We gratefully acknowledge the support of Intel Corporation and NSF CCRI 2016701, NSF CNS 1815047 for providing FPGA resources.  ... 
arXiv:2110.10857v1 fatcat:bxjizz5hx5dzrft4qb4nhkbdqa

An adaptively reconfigurable computing framework for intelligent Robotics

Moazzam Hussain, Ahmad Din, Massimo Violante, Basilio Bona
2011 2011 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM)  
We present an in-depth evaluation of proposed architecture in terms of its benefits in area, power consumption and timings.  ...  Keywords-Micro UAV, FPGA, partial reconfiguration, hardware platform, post disaster assesment.  ...  Each component is wired in a way that its input clock can be disabled to reduce power consumption and is controlled by the RISC Processor.  ... 
doi:10.1109/aim.2011.6026990 fatcat:37ainvayrfhtxhsp6i3dckqmsy

FPGA-extended General Purpose Computer Architecture [article]

Philippos Papaphilippou, Myrtle Shah
2022 arXiv   pre-print
Finally, the feasibility of adopting the proposed architecture in today's CPUs is studied through the prototyping of fast-reconfigurable FPGAs and studying the miss behaviour of opcodes.  ...  Small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom or standardised instructions.  ...  4.2 and 4.3, we present an example fast-reconfigurable FPGA architecture and prototype it in simulation.  ... 
arXiv:2203.10359v3 fatcat:bg2wfnqbafb4vlrfg54kfude5u
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