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Simultaneous buffer and wire sizing for performance and power optimization

J. Cong, Cheng-Kok Koh, Kwok-Shing Leung
Proceedings of 1996 International Symposium on Low Power Electronics and Design  
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions.  ...  This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions  ...  Charles Chien and Prof. Rajeev Jain at UCLA EE Department for providing the transceiver chip, and Mr. Takumi Okamoto and Mr. Lei He for their helpful discussions.  ... 
doi:10.1109/lpe.1996.547521 dblp:conf/islped/CongKL96 fatcat:ulj2aefxbngonfrcuv5vlbu3my

Power-optimal simultaneous buffer insertion/sizing and wire sizing

Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS).  ...  We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty.  ...  CONCLUSION We have analyzed the optimal power dissipation problems for simultaneous buffer insertion/sizing and wire sizing with delay constraints.  ... 
doi:10.1109/iccad.2003.159741 fatcat:fje4sawtwjgv3hukthodgbzpru

Simultaneous analytic area and power optimization for repeater insertion

G.S. Garcea, N.P. van der Meijs, R.H.J.M. Otten
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Besides exploring optimal area, power and performance trade-offs for uniform buffer inseltion, this tool can he used for the screening of critical segments when the buffers are positionconstrained.  ...  Given a certain wire geometry (width and layer assignment) and a factor K, we derive repeater sizes and segment lengths that simultaneously minimize silicon device area and power dissipation associated  ...  Therefore, areaminimization for a certain performance simultaneously minimizes power for that performance. Stated otherwise, (IO) and (11) not only minimize area but also power.  ... 
doi:10.1109/iccad.2003.159739 fatcat:pq43ll2w45c2nllgdbogiisrca

A PARTICLE SWARM OPTIMIZATION APPROACH FOR LOW POWER VERY LARGE SCALE INTEGRATION ROUTING

Nallathambi
2014 Journal of Mathematics and Statistics  
The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires.  ...  The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis.  ...  Science Publications JMSS CONCLUSION The optimal power dissipation for simultaneous buffer insertion and buffer sizing and wire sizing with shortest path constraints using PSO algorithm for VLSI interconnect  ... 
doi:10.3844/jmssp.2014.58.64 fatcat:2jknr3dg7vfwrpfvyutmha6urq

Optimization of power dissipation and skew sensitivity in clock buffer synthesis

Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Lin
1995 Proceedings of the 1995 international symposium on Low power design - ISLPED '95  
Our efficient algorithm optimizes power dissipation and clock skew sensitivity simultaneously.  ...  We introduce a new design concept and an algorithm to optimize both power dissipation and skew sensitivity in the clock buffer synthesis.  ...  Cong and Koh [5] proposed a simultaneous driver and wire sizing algorithm for delay and power dissipation minimization.  ... 
doi:10.1145/224081.224113 dblp:conf/islped/ChungKCL95 fatcat:daq2nyipbjfydhczpu5i66dkvy

Zero Skew Clock-Tree Optimization With Buffer Insertion/Sizing and Wire Sizing

J.-L. Tsai, T.-H. Chen, C.C.-P. Chen
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we present ClockTune, a simultaneous buffer insertion/sizing and wire-sizing algorithm which guarantees zero skew and minimizes delay and power in polynomial time.  ...  Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long been considered intractable.  ...  We now define another transformation for simultaneous buffer insertion/sizing and wire sizing.  ... 
doi:10.1109/tcad.2004.825875 fatcat:7gg3e7ahjvb5dhyyrbitv5qgge

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Jeng-Liang Tsai, Charlie Chung-Ping Chen
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
, buffer-sizing, and wire-sizing.  ...  Skew and delay optimization for reliable buffered clock trees. In  ...  The initial routings are then optimized for process-variation and power with a novel algorithm that performs simultaneous buffer-insertiodsizing and wire-sizing within the zero-skew design-space.  ... 
doi:10.1145/1120725.1120932 dblp:conf/aspdac/TsaiC05 fatcat:bbtujlqztzarlpuouhggpb7oza

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
2002 VLSI design (Print)  
We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees.  ...  Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity.  ...  We present in this paper an algorithm for simultaneously optimizing the above-mentioned objectives by sizing wires and buffers in clock trees.  ... 
doi:10.1080/1065514021000012200 fatcat:yupibqqx3feodipj5jvx3waoja

Fast interconnect synthesis with layer assignment

Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, have proven to be the critical part of a successful timing closure optimization tool.  ...  Techniques for simultaneous layer assignment and buffer insertion with resource control are increasingly important for the quality of results of interconnect synthesis.  ...  (a) Simultaneous buffer insertion and continous wire sizing.(b) Simultaneous buffer insertion and taperd wire sizing (TWS). (c) Simultaneous buffer insertion and uniform wire sizing (UWS).  ... 
doi:10.1145/1353629.1353648 dblp:conf/ispd/LiAHMQV08 fatcat:ezztjdz3mndall3kgqsfi4nrfi

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Zhang-Ming Zhu, Bao-Tian Hao, Yin-Tang Yang, Yue-Jin Li
2010 Chinese Physics B  
Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth  ...  Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.  ...  [3] for determining the optimal wire sizing of buffered global interconnects and the impact of wire width and space on performance was investigated.  ... 
doi:10.1088/1674-1056/19/12/127805 fatcat:yfjvfhkkenfmpgwmpzuatt5rua

Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks

Rupak Samanta, Jiang Hu, Peng Li
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this work, we investigate how to optimize such clock networks through buffer and wire sizing. A two-stage hybrid optimization approach is proposed.  ...  It considers the realistic constraint of discrete buffer/wire sizes and is based on accurate delay models.  ...  Venkataraman at Magma Design Automation for providing clock trees for ISCAS89 and r1-r5 benchmarks and G.  ... 
doi:10.1109/tvlsi.2009.2019088 fatcat:ysakntuvrbbqrfgaqmmi2lla4y

Discrete buffer and wire sizing for link-based non-tree clock networks

Rupak Samanta, Jiang Hu, Peng Li
2008 Proceedings of the 2008 international symposium on Physical design - ISPD '08  
In this work, we investigate how to optimize such clock networks through buffer and wire sizing. A two-stage hybrid optimization approach is proposed.  ...  It considers the realistic constraint of discrete buffer/wire sizes and is based on accurate delay models.  ...  Venkataraman at Magma Design Automation for providing clock trees for ISCAS89 and r1-r5 benchmarks and G.  ... 
doi:10.1145/1353629.1353667 dblp:conf/ispd/SamantaHL08 fatcat:qd7gheivwbgwpdg5ukec7g4qaa

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Charles Alpert, Chris Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli Kashyap, Stephen Quay
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on  ...  Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously.  ...  Several works have also proposed simultaneous buffer insertion and wire sizing optimization.  ... 
doi:10.1145/505411.505414 fatcat:fzidivjps5gsbdqf5mx6saln4u

Simultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique

C. Alpert, C. Chu, G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. Quay
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on  ...  Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously.  ...  Several works have also proposed simultaneous buffer insertion and wire sizing optimization.  ... 
doi:10.1109/tcad.2003.819910 fatcat:ulz7j63xmbazpbxpkl7njgmg3u

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

Charles Alpert, Chris Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli Kashyap, Stephen Quay
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on  ...  Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously.  ...  Several works have also proposed simultaneous buffer insertion and wire sizing optimization.  ... 
doi:10.1145/505388.505414 dblp:conf/ispd/AlpertCGHHKQ02 fatcat:shleqzhnffd73m5vc2fmbbfzje
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