Filters








9,980 Hits in 18.7 sec

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
2022 Proceedings of the 2022 International Symposium on Physical Design  
design flows due to the high circuit complexity and sensitivity to layout parasitics.  ...  Despite continuous efforts in layout automation for full-custom circuits, including analog/mixed-signal (AMS) designs, automated layout tools have not yet been widely adopted in current industrial full-custom  ...  ACKNOWLEDGEMENT This work is supported in part by NVIDIA Corporation, the DARPA IDEA program, and the NSF under Grant No. 1704758.  ... 
doi:10.1145/3505170.3511044 fatcat:tovuba5ac5hj7msttbdgouf7ku

Issues and strategies for the physical design of system-on-a-chip ASICs

T. R. Bednar, P. H. Buffet, R. J. Darden, S. W. Gould, P. S. Zuchowski
2002 IBM Journal of Research and Development  
An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.  ...  The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully  ...  The authors would like to specifically acknowledge Paul Dunn and Pat Ryan for data volume test-case results. SA-27E SoC chip design (buffer holes enlarged for better visibility).  ... 
doi:10.1147/rd.466.0661 fatcat:b6inezmumzaxxl2wspgqtxt64u

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

Göran Jerke, Jens Lienig, Jürgen Scheible
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
It is especially tailored to overcome the lack of current-flow consideration within existing routing tools.  ...  We present a new approach that addresses this electromigration issue by considering current density and inhomogeneous current-flow within arbitrarily shaped metallization patterns during physical design  ...  The authors can be contacted by email: goeran.jerke@ieee.org, jens@ieee.org, juergen.scheible@de.bosch.com The authors wish to thank Gerd Haist, Manfred Henning and Ralf-Eckhard Stephan from Robert Bosch  ... 
doi:10.1145/996566.996618 dblp:conf/dac/JerkeLS04 fatcat:i23tdn2i4nc6lpsixslk2phety

Automation of Analog IC Layout

Juergen Scheible, Jens Lienig
2015 Proceedings of the 2015 Symposium on International Symposium on Physical Design - ISPD '15  
We will then introduce active and open research areas and present two visions -a "continuous layout design flow" and a "bottom-up meets top-down design flow" -which could significantly push analog design  ...  This shortfall is primarily rooted in the analog IC design problem itself, which is considerably more complex even for small problem sizes.  ...  ACKNOWLEDGEMENTS We would like to thank Daniel Marolt, Andreas Krinke, Vinko Marolt and Göran Jerke for the numerous fruitful discussions related to the topic of this paper.  ... 
doi:10.1145/2717764.2717781 dblp:conf/ispd/ScheibleL15 fatcat:jn6xkaklcrf4tpkvqgdgxelloq

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

F. Baskaya, D.V. Anderson, Sung Kyu Lim
2009 IEEE Transactions on Circuits and Systems - II - Express Briefs  
With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design  ...  indispensable step of the analog physical synthesis flow.  ...  Simultaneous Placement and Routing Placement and routing for analog design differs from those for digital design.  ... 
doi:10.1109/tcsii.2009.2023351 fatcat:jnzewn7yhbhivow46ssiobk4ca

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

2021 Informacije midem  
This paper presents a new placement and routing method for layout generation of CMOS operational amplifiers (op-amps). Both circuit sizing and layout generation stages are performed automatically.  ...  CMOS technology with 1.8 V supply voltage are presented.  ...  Current-density to determine the segment width and design rules are the constraints in the routing stage.  ... 
doi:10.33180/infmidem2021.304 fatcat:p23djdxgofbujk6hvrkd4ccrde

Addressing thermal and power delivery bottlenecks in 3D circuits

Sachin S. Sapatnekar
2009 2009 Asia and South Pacific Design Automation Conference  
The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared  ...  This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per  ...  MIM capacitors are fabricated between metal layers, and have high capacitance density and low leakage current density.  ... 
doi:10.1109/aspdac.2009.4796518 dblp:conf/aspdac/Sapatnekar09 fatcat:imewooenszg6pgrm6bcoyb7nl4

Designing mega-ASICs in nanogate technologies

David E. Lackey, Paul S. Zuchowski, Juergen Koehl
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas  ...  discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities  ...  While power densities have increased or remained the same due to thermal considerations [19] , the supply voltage has continued to scale. This results in more current-per-unit-area on the chip.  ... 
doi:10.1145/775832.776029 dblp:conf/dac/LackeyZK03 fatcat:3zyqburjkrcmpmwvmemgjnmwiu

Designing mega-ASICs in nanogate technologies

David E. Lackey, Paul S. Zuchowski, Juergen Koehl
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas  ...  discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities  ...  While power densities have increased or remained the same due to thermal considerations [19] , the supply voltage has continued to scale. This results in more current-per-unit-area on the chip.  ... 
doi:10.1145/776028.776029 fatcat:ba4ii7i3wrfl5i77f262ebd55y

An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction [chapter]

Jasmine Kaur Gulati, Bhanu Prakash, Sumit Darak
2017 Communications in Computer and Information Science  
With the advancement towards the deep sub-micron technology, the SoC design consists of components that prompt to a higher power density.  ...  As a result, the clock network shows increment in core utilization, improvement in routing, reduction in power consumption and timing violations.  ...  Acknowledgements This study would not have been successful without the support and direction of number of people who have contributed and assisted in the completion of my thesis work in multiple ways.  ... 
doi:10.1007/978-981-10-7470-7_56 fatcat:fyvgrftno5fn7ggllygkvlqyiu

Modeling and design for beyond-the-die power integrity

Yiyu Shi, Lei He
2010 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
This paper provides a tutorial of modeling and design for beyond the die power integrity.We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs.  ...  We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.  ...  I/O Planning and Placement I/O planning and placement plays a key role as the interface between chip and package designs in a co-design flow.  ... 
doi:10.1109/iccad.2010.5653721 dblp:conf/iccad/ShiH10 fatcat:lbt5mjetgnh6djs7vxqefzzrom

Design Automation for Digital Microfluidic Biochips

Tsung-Yi Ho
2014 IPSJ Transactions on System LSI Design Methodology  
With the assistance of CAD tools, users can concentrate on the development and abstraction of nanoscale bioassays while leaving chip optimization and implementation details to CAD tools.  ...  Basic microfluidic operations, such as mixing and dilution, are performed on the array, by routing the corresponding droplets on a series of electrodes.  ...  On the other hand, in (b), simultaneous consideration of electrode addressing and routing provides a higher feasibility and quality routing solution in terms of routability and wirelength.  ... 
doi:10.2197/ipsjtsldm.7.16 fatcat:6cskxmi2szbrtiyyiabqpry4uy

Constraint-Based Layout-Driven Sizing of Analog Circuits

Husni Habal, Helmut Graeb
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The new flow combines placement and routing algorithms from the state of the art with new concepts to create a functional and robust circuit layout.  ...  technologies and must be taken into consideration during analog circuit design [WVN + 06].  ... 
doi:10.1109/tcad.2011.2158732 fatcat:schj7wh4fnfazepnii5cgywpfa

Comparison of analog and digital nanosystems: Issues for the nano-architect

Pritish Narayanan, Teng Wang, Michael Leuchtenburg, Csaba Andras Moritz
2008 2008 2nd IEEE International Nanoelectronics Conference  
It is seen that while an analog nanoscale implementation of the CNN may be difficult with self-assembly based approaches given the requirements for customization of devices and arbitrary routing, a digital  ...  A specialized architecture for CNN with Resonant Tunneling Diodes (RTD) is also discussed.  ...  Arbitrary placement of devices and routing of signals is not likely possible in such systems.  ... 
doi:10.1109/inec.2008.4585654 fatcat:4tpcktarxvdpfjlfyuox35zt3e

Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability [chapter]

Jarrod A. Roy, David A. Papa, Igor L. Markov
2007 Series on Integrated Circuits and Systems  
The most recent work on Capo has been on improving Capo's performance on routing benchmarks and difficult instances of floorplanning and mixed-size placement, and transforming Capo into an incremental  ...  Empirical results show that Capo's incremental placement moves objects minimally, produces solutions with good HPWL, and runs faster than other available legalization techniques [36] .  ...  When routed with Cadence WarpRoute, uniform whitespace produces 3.95% overfull global routing cells and routes in just over 5 hours with 120 violations.  ... 
doi:10.1007/978-0-387-68739-1_5 fatcat:pkp6oufrarc4fcml2cgo7lcw3q
« Previous Showing results 1 — 15 out of 9,980 results