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Simultaneous circuit transformation and routing

H. Yoshida, M. Sera, M. Kubo, M. Fujita
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design  
In this paper, we propose a new methodology to integrate circuit transformation into routing.  ...  More specifically, this paper shows an approach for performing routing and wire reconnection simultaneously.  ...  Simultaneous Wire Reconnection and Routing In this section, we present an exact approach for solving the reconnection and routing problems simultaneously.  ... 
doi:10.1109/aspdac.2002.994966 dblp:conf/vlsid/YoshidaSKF02 fatcat:pa2judhi3bdrdkxibrimlqo2bm

Analysis of Transients during the Power System Restoration

Žaneta Eleschová, Martin Jedinák, Rastislav Šmidovič
2018 Transactions on Electrical Engineering  
The Defence plan and Restoration plan development is a part of transmission system operator's responsibilities and requires thorough calculations, simulations and publication of instructions.  ...  The plans focus on extensive failures that have a heavy impact on the system operation and could lead to a blackout.  ...  In the following figures the voltages and currents are plotted. Simultaneous route creation Gradual route creation Simultaneous route creation Gradual route creation Fig. 9 .  ... 
doi:10.14311/tee.2018.4.073 fatcat:4k3cds2wazcklfgrdr5j6q4vr4

How much can logic perturbation help from netlist to final routing for FPGAs

Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
2007 Proceedings - Design Automation Conference  
This idea of perturbing logic between the free LUT-internal and critical LUT-external circuit resources is simple and proved to be powerful.  ...  Using rewiring technique for such logic perturbations, we show that significant cut-downs upon already excellent results from the state-of-the-art DAOmap mappings and the TVPR place-and-route can still  ...  We take the transformations one by one and evaluate the transformed circuit with a pseudo technology mapping.  ... 
doi:10.1145/1278480.1278707 dblp:conf/dac/ZhouTLW07 fatcat:bmgqgek6drelhkitab2tf6kbqu

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
2007 Proceedings - Design Automation Conference  
This idea of perturbing logic between the free LUT-internal and critical LUT-external circuit resources is simple and proved to be powerful.  ...  Using rewiring technique for such logic perturbations, we show that significant cut-downs upon already excellent results from the state-of-the-art DAOmap mappings and the TVPR place-and-route can still  ...  We take the transformations one by one and evaluate the transformed circuit with a pseudo technology mapping.  ... 
doi:10.1109/dac.2007.375296 fatcat:fb6s5savx5cptbjei3igd3mcla

A tensor model of multipath routing based on multiple QoS metrics

Olexandr V. Lemeshko, Oksana Yu. Yevseyeva O., Sergey V. Garkusha
2013 2013 International Siberian Conference on Control and Communications (SIBCON)  
Index Terms-tensor model, routing, quality of service, packet loss.  ...  Flow model for multipath routing with guaranteed the quality of service (QoS) is proposed.  ...  (circuits and node pairs).  ... 
doi:10.1109/sibcon.2013.6693645 fatcat:odgquznbnzfcpavc2kye2jwtb4

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery [chapter]

Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X. -D. Tan, Zhu Pan
2004 Lecture Notes in Computer Science  
We apply a time-domain merged adjoint network to efficiently compute the gradients and a novel equivalent circuit modeling technique to speed up the optimization process.  ...  In this paper, we present an efficient method to simultaneously size wire widths and decoupling capacitance (decaps) areas for optimizing power/ ground (P/G) networks modeled as RLC linear networks subject  ...  Because wires consume the routing resource while decaps cost spare die area, algorithm that can simultaneously optimize both of them is needed to reach the best tradeoff between routing resource and die  ... 
doi:10.1007/978-3-540-30205-6_45 fatcat:peaeyhq635dzjc3spzuidkd43u

A new FPGA detailed routing approach via search-based Boolean satisfiability

Gi-Joon Nam, K.A. Sakallah, R.A. Rutenbar
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
unroutability of a given circuit by demonstrating the absence of a satisfying assignment to the routing Boolean function.  ...  Boolean-based routing methods transform the geometric FPGA routing task into a large but atomic Boolean function with the property that any assignment of input variables that satisfies the function specifies  ...  Betz and G. Lemieux of the University of Toronto for providing benchmark circuits for the experiments.  ... 
doi:10.1109/tcad.2002.1004311 fatcat:v4rvw5ztybf7pcfwuxt6lt2ele

A 76–84 GHz SiGe Power Amplifier Array Employing Low-Loss Four-Way Differential Combining Transformer

Mury Thian, Marc Tiebout, Neil B. Buchanan, Vincent F. Fusco, Franz Dielacher
2013 IEEE transactions on microwave theory and techniques  
It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits.  ...  A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with  ...  Importantly, these transformers can also simultaneously provide an impedance transformation (the higher the number of input ports, the higher the impedance transformation ratio) and balanced-to-unbalanced  ... 
doi:10.1109/tmtt.2012.2231425 fatcat:4owebl5exbeibpffzvhzobh5ui

A min-cost flow based detailed router for FPGAs

Seokjin Lee, Yongseok Cheon, M.D.F. Wong
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
The Lagrangian relaxation approach transforms the routing problem into a sequence of Lagrangian subproblems.  ...  Using the min-cost flow approach, our algorithm routes all the nets connected to a common logic module simultaneously.  ...  By node splitting transformation, any node i with nonzero cost and capacity is transformed into the two nodes i and i .  ... 
doi:10.1109/iccad.2003.159716 fatcat:32q4i6cfj5bhxn3iqidjrmbsui

Postlayout logic restructuring using alternative wires

Shih-Chieh Chang, Kwang-Ting Cheng, Nam-Sung Woo, M. Marek-Sadowska
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The approach attempts to identify alternative wires and alternative functions for wires that cannot be routed due to the limited routing resources in FPGA.  ...  The proposed synthesis technique can also be applied to standard cell and gate array designs to reduce the routing area.  ...  For example, in the circuit depicted in Fig. 1 (from [5] ), we can remove wire by simultaneously adding wires and .  ... 
doi:10.1109/43.640617 fatcat:xqtamzigozgidigzchzt7nbfzq

Optimization of Delivery Routes using the Little´s Algorithm

Rudolf Kampf, Institute of Technology and Business in České Budějovice Faculty of Technology, Department of Transport and Logistics, Czech Republic
2018 Naše More (Dubrovnik)  
Optimization of the delivery route was carried out using the Little´s law. The optimization resulted in a total saving of 312 km per year.  ...  Omitting i -row and j -column of the reduced distance matrix and simultaneous exclusion of the return route (i.e. the route from j -point to i -point) by marking the relevant field of the "forbidden" route  ...  was a total saving of 6 km per one circuit route.  ... 
doi:10.17818/nm/2018/4si.13 fatcat:utblvi5akrhj3mql25tmzoye3a

A novel bidirectional DC-DC converter with high efficiency and small size AC link

Katsuji Iida, Hirofumi Matsuo, Toshiro Hirose, Yoichi Ishizuka
2009 INTELEC 2009 - 31st International Telecommunications Energy Conference  
The transformer is not used to isolate the input and output power circuit.  ...  The main feature of the proposed circuit is that the power processed by two inverters and a transformer is only half of the electric power transmitted.  ...  Fig. 7 7 Current-route and it's equivalent circuit in state b Fig. 8 . 8 Current-route and it's equivalent circuit in state c state.  ... 
doi:10.1109/intlec.2009.5351737 fatcat:xqwklzzybzg6tepfqiybrmtkgu

Glossary [chapter]

2011 High Voltage Protection for Telecommunications  
These transformers or reactors are primarily used to protect telecommunication or control circuits at power stations or along routes exposed to power line induction or both.  ...  Neutralizing transformers and reactors: Devices that introduce a voltage into a circuit pair that opposes an unwanted voltage.  ... 
doi:10.1002/9781118127018.gloss fatcat:ynnahsse5zefxb5efxqzb32uay

A Parallel Processing System for a High-Speed Printed Document Recognition

Kyung-Ae Moon, Hyung Lee, Hee-Jun Yoon, Jong-Won Park
1996 IAPR International Workshop on Machine Vision Applications  
This paper transforms a serial recognition algorithm using a mesh feature for the printed characters into the parallel algorithm, proposes a parallel processor systkm and a parallel memory system for the  ...  parallel algorithm, and simulates the function and the performance of the system by using a CADENCE simulation program.  ...  Address a n d d a t a r o u t i n g The address routing circuit receives m addresses from the register A1 in the address calculating circuit and moves the m addresses to the m memory modules through the  ... 
dblp:conf/mva/MoonLYP96 fatcat:i5ccy43gdvforo62rx6a7hwmzq

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search [chapter]

Gi-Joon Nam, Karem Sakallah, Rob Rutenbar
2002 Lecture Notes in Computer Science  
The proposed algorithm named search-SAT is implemented and applied to real-world industry circuits.  ...  In this paper, we revisit the SAT-based routing idea for FPGA routing, and propose a new hybrid algorithm that integrates SAT-based FPGA routing with a conventional geometric search FPGA router.  ...  the advantages such as simultaneous net embedding and routability decision.  ... 
doi:10.1007/3-540-46117-5_38 fatcat:5bnf5vwofzh3zox5eqb3r4rglu
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