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Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin (+2 others)
2008 Solid-State Electronics  
In this work, we have fabricated and characterized the 3-dimensional fin SONOS flash memory. This device has two independent gates on both sides of Si-fin and each of them governs two side-channels.  ...  Fabrication flow and array structure are described as well as operation schemes. The 4-bit/cell operation is demonstrated with the multi-bit concept in fabricated devices.  ...  Acknowledgement This work was supported by Samsung Electronics with a project entitled as 'The Research on Structure and Characteristics of the Nonvolatile Memory Devices'.  ... 
doi:10.1016/j.sse.2008.06.021 fatcat:ryqyokdpvraafj2s5gsjgyxpci

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

Woei-Cherng Wu, Tien-Sheng Chao, Wu-Chin Peng, Wen-Luh Yang, Jian-Hao Chen, Ming Wen Ma, Chao-Sung Lai, Tsung-Yu Yang, Chien-Hsing Lee, Tsung-Min Hsieh, Jhyy Cheng Liou, Tzu Ping Chen (+4 others)
2007 Semiconductor Science and Technology  
In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated.  ...  The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results.  ...  Using MLC, the density of a flash memory device would be doubled, without any increase in the die size.  ... 
doi:10.1088/0268-1242/23/1/015004 fatcat:hmfuznjdsral7alq7llpz4zpxa

Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate

2006 IEICE transactions on electronics  
A 2-bit operational metal/silicon-oxide-nitride-oxidesilicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density.  ...  , flash memory, asymmetric double gate, nonvolatile memory  ...  Acknowledgments This work was supported in part by Samsung Electronics Co., Ltd., and in part by the National Research Program for the 0.1-Terabit Nonvolatile Memory Development, sponsored by the Korea  ... 
doi:10.1093/ietele/e89-c.5.578 fatcat:s3hrss24krcbnp3qhhovmfya4e

Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance [chapter]

Sung-Jin Choi, Yang-Kyu Choi
2011 Flash Memories  
To this end, aggressive scaling of the device dimension and multi-level cell (MLC) or multi-bit cell (MBC) have been proposed in NAND and NOR Flash memory architectures.  ...  Introduction There is strong demand to maintain the trend of increasing bit density and reducing bit cost in Flash memory technology.  ...  Flash Memories How to reference In order to correctly reference this scholarly work, feel free to copy and paste the following: Sung-Jin Choi and Yang-Kyu Choi (2011) .  ... 
doi:10.5772/18460 fatcat:envuysngyfejrj2jxysxeinkku

Metal nanocrystals as charge storage nodes for nonvolatile memory devices

P.H. Yeh, L.J. Chen, P.T. Liu, D.Y. Wang, T.C. Chang
2007 Electrochimica Acta  
The memory effects of the metal nanocrystals were found to be more pronounced than those of the semiconductor nanocrystals. Various metal nanocrystals as charge storage nodes are reviewed.  ...  By tunneling dielectrics engineering, the optimum I G Write/Erase /I G Retention ratio can be obtained.  ...  Acknowledgments Part of the work was performed at National Nano Device Laboratory.  ... 
doi:10.1016/j.electacta.2006.09.006 fatcat:4sv7oacmbfdvzaj32paw3kvn7i

State-of-the-art flash memory devices and post-flash emerging memories

ChihYuan Lu, HangTing Lue, YiChou Chen
2011 Science China Information Sciences  
Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm.  ...  Flash memory.  ...  VSAT [24] uses a multi U-turn channel, and vertical gate (VG) [25, 26] uses a horizontal channel but vertical double-gate device.  ... 
doi:10.1007/s11432-011-4221-z fatcat:zpqszuxdlfc3pop6s6w6k7o5ly

Flash Memory Scaling: From Material Selection to Performance Improvement

Tuo-Hung Hou, Jaegoo Lee, Jonathan T. Shaw, Edwin C. Kan
2008 Materials Research Society Symposium Proceedings  
Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure.  ...  In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm 2 ) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated  ...  Both are critical in optimizing memory P/E and retention characteristics.  ... 
doi:10.1557/proc-1071-f02-01 fatcat:dr3ik3pq2vewhdzsifl4cvr6zq

Modeling floating body Z-RAM storage cells

Viktor Sverdlov, Siegfried Selberherr
2010 2010 27th International Conference on Microelectronics Proceedings  
First, a Z-RAM cell based on a 50nm gate length double-gate structure corresponding to state of the art technology is studied.  ...  Advanced floating body Z-RAM memory cells are studied. In particular, the scalability of the cells is investigated.  ...  Recently a 10 nm bulk-planar SONOS type memory cell with a double tunnel junction, exhibiting good scalability while offering low write/erase voltages and excellent charge retention characteristics at  ... 
doi:10.1109/miel.2010.5490533 fatcat:fmyfbnjljrgaflxn6uqcmoguc4

Semiconductor Nanowire MOSFETs and Applications [chapter]

Hao Zhu
2017 Nanowires - New Insights  
Effective integration of nanowires in modern complementary metal-oxide-semiconductor (CMOS) technology, specifically in MOSFET devices, and non-volatile memory applications is also reviewed.  ...  Employing nanowire as metal-oxide-semiconductor field-effect transistor (MOSFET) channel can enable a gate-surrounding structure allowing an excellent electrostatic gate control over the channel for reducing  ...  Author details Hao Zhu Address all correspondence to: School of Microelectronics, Fudan University, Shanghai, P.R. China  ... 
doi:10.5772/67446 fatcat:qeakdats2reazddd7xgtga35pu

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Joo Yun Seo, Yoon Kim, Sang-Ho Lee, Daewoong Kwon, Hee-Do Na, Hyun Chul Sohn, JongHo Lee, Byung-Gook Park
2019 2019 Electron Devices Technology and Manufacturing Conference (EDTM)  
To adopt high-κ layer into 3D NAND, its memory characteristics were evaluated with capacitors and gate-all-around flash memory devices.  ...  In Chapter 3, the memory characteristics of high-κ layer were evaluated with fabricated capacitors and flash memory devices.  ...  Consequently, BiCS flash memory cannot utilize various advantages of metal gate SONOS cell structure, for example, faster erase speed, wider Vth margin, and better retention characteristics.  ... 
doi:10.1109/edtm.2019.8731328 fatcat:sc4eunm44bccffmfpzjfuplqea

Evolutionary Memory: Unified Random Access Memory (URAM) [chapter]

Yang-Kyu Choi, Jin-Woo H
2010 Advances in Solid State Circuit Technologies  
Operational principle of a SONOS Flash memory. (a) schematic of SONOS structure and (b) drain current versus gate voltage characteristics for two data states.  ...  Flash memory characteristics Flash memory performance is normally evaluated in terms of four aspects: program speed, erase speed, data retention time, and endurance cycles.  ... 
doi:10.5772/8622 fatcat:et4rolj62jbkllx6m6rh44se44

Towards Polyoxometalate-Cluster-Based Nano-Electronics

Laia Vilà-Nadal, Scott G. Mitchell, Stanislav Markov, Christoph Busche, Vihar Georgiev, Asen Asenov, Leroy Cronin
2013 Chemistry - A European Journal  
Xavier López for fruitful discussion and valuable suggestions made during the preparation of this work.  ...  We would like to express our gratitude to The Quantum Chemistry Group of the Universitat Rovira i Virgili (URV), Tarragona, for computational resources. We wish to acknowledge Dr.  ...  Indeed, our hierarchical device simulations, incorporating the output of DFT simulations in a model memory cell, confirm the viability of a POM-floating gate in a multi-bit memory.  ... 
doi:10.1002/chem.201301631 pmid:24281797 fatcat:3t3dpnorv5gzpo74eqnnbz43ey

Future Memory Technology and Ferroelectric Memory as an Ultimate Memory Solution [chapter]

Kinam Kim, Dong Jin
2011 Ferroelectrics - Applications  
However, EEPROM has the same limitations in flash memory due to structural and operational similarity of the unit memory cell in flash memory.  ...  With this approach, they can achieve several essential properties for NAND flash memory: reasonable programming/erasing characteristics, an adequate V PASS window for multi-bit operation and robust reliability  ...  In particular, the use of these materials as varying capacitors, gyroscope, acoustics sensors and actuators, microgenerators and memory devices will be exposed, providing an up-to-date review of recent  ... 
doi:10.5772/18550 fatcat:eqfywnhnvfftzly7osacjesu7q

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

G. Molas, M. Bocquet, J. Buckley, H. Grampeix, M. Gély, J.P. Colonna, F. Martin, P. Brianceau, V. Vidal, C. Bongiorno, S. Lombardo, G. Pananakakis (+3 others)
2008 Microelectronic Engineering  
In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories.  ...  Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties.  ...  the retention compared to SONOS (Si-SiO 2 -SiN-SiO 2 -Si) memories.  ... 
doi:10.1016/j.mee.2008.09.008 fatcat:jbe5y7qkirbbxdlhtlzokufjzm

Nonvolatile Memories Based on Graphene and Related 2D Materials

Simone Bertolazzi, Paolo Bondavalli, Stephan Roche, Tamer San, Sung-Yool Choi, Luigi Colombo, Francesco Bonaccorso, Paolo Samorì
2019 Advanced Materials  
Herein, an overview of graphene and related 2D materials (GRMs) in different types of NVM cells is provided, including resistive random-access, flash, magnetic and phase-change memories.  ...  As silicon-based flash memories are approaching their fundamental limit, vertical stacking of multiple memory cell layers, innovative device concepts, and novel materials are being investigated.  ...  3D flash memories consisting of multi-stacked arrays of memory cells  ... 
doi:10.1002/adma.201806663 pmid:30663121 fatcat:3pok26mmk5aqxpxb3k3hubcnh4
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