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Simulating Shared Memory in Real Time: On the Computation Power of Reconfigurable Architectures

Artur Czumaj, Friedhelm Meyer auf der Heide, Volker Stemann
1997 Information and Computation  
We consider randomized simulations of shared memory on a distributed memory machine (DMM) where the n processors and the n memory modules of the DMM are connected via a reconfigurable architecture.  ...  It was already known that an n_m reconfigurable mesh can simulate in constant time an n-processor CRCW PRAM with shared memory of size m.  ...  ACKNOWLEDGMENT We are grateful to Assaf Schuster for pointing out the problem of simulations on a reconfigurable mesh. Received February 22, 1996; final manuscript received March 25, 1997  ... 
doi:10.1006/inco.1997.2642 fatcat:6p23hty4wvdqhoeq5az2c4hxp4

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation

Gang Chen, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov, Feng Li
2016 Microprocessors and microsystems  
Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance.  ...  In this paper, we present a reconfigurable cache architecture which supports dynamic cache partitioning at hardware level and a framework that can exploit cache management for real-time MPSoCs.  ...  This prototype will bridge the gap between simulation and real systems, and will serve us a real (not simulation) reconfigurable cache for studying and validating cache management strategies on the real-time  ... 
doi:10.1016/j.micpro.2015.11.020 fatcat:paful55lavd3rbabcz6x7uf2aa

Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs

Gang Chen, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov
2014 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)  
How to manage the shared cache for real-time multi-core systems in order to optimize the system performance while guaranteeing the system predictability is still an open issue.  ...  Shared cache in modern multi-core systems has been considered as one of the major factors that degrade system predictability and performance.  ...  This will serve us a real (not simulation) reconfigurable cache for studying and validating cache management strategies on the real-time multi-core system under different cache settings. III.  ... 
doi:10.1109/reconfig.2014.7032502 dblp:conf/reconfig/ChenH0KHLS14 fatcat:43uxjzroqzchloxppdwclv2c7a

Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures

Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan
2007 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)  
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high performance, high flexibility  ...  The research lays a foundation for further exploration of multithreading on multiple target architectures. 2007 International Symposium on Field-Programmable Custom Computing Machines 0-7695-2940-2/07  ...  The comparison is based on simulation time per frame, data memory and code memory requirement. The italic values represent the overheads introduced by the OS.  ... 
doi:10.1109/fccm.2007.30 dblp:conf/fccm/WeiMNAE07 fatcat:jiuapyby7zbfle3bt772a5zwra

Run-Time Reconfigurable FFT Engine

Ahmad F. Al-Allaf, Shefa A. Dawwd
2010 مجلة النهرين للعلوم الهندسية  
These two dimensions are optimized based on using run time reconfiguration, double buffering technique and the hardware virtualization to reuse the available processing components.  ...  This approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput).  ...  The unregistered version of Win2PDF is for evaluation or non-commercial use only.  ... 
doaj:a3cd7a3bea89464595260e3dc19e4672 fatcat:v6x4hexgv5ahlnmhmr7a73huti

A hardware-software real-time operating system framework for SoCs

V.J. Mooney, D.M. Blough
2002 IEEE Design & Test of Computers  
SoC) architecture with reconfigurable logic and multiple processing elements sharing a common memory, like that shown in Figure 1 , is likely to become quite common in the near future.  ...  However, changing the SoC architecture and associated software can require significant re-porting or reconfiguration of the real-time operating system.  ...  Akgul, Jaehwan Lee, Kyoung-Keol Ryu, Mohamed Shalan, Pun Shiu, Eung Shin, Di-shi Sun, and Yudong Tan, who did much of the work reported in this article.  ... 
doi:10.1109/mdt.2002.1047743 fatcat:cfr6xhfbljgjbmvbdp2nqaz35e

A reconfigurable real-time SDRAM controller for mixed time-criticality systems

Sven Goossens, Jasper Kuijsten, Benny Akesson, Kees Goossens
2013 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)  
Verifying real-time requirements of applications is increasingly complex on modern Systems-on-Chips (SoCs). More applications are integrated into one system due to power, area and cost constraints.  ...  The main contributions are: 1) A run-time reconfigurable SDRAM controller architecture, which allows trade-offs between guaranteed bandwidth, response time and power. 2) A methodology for offering composable  ...  However, no bounds on performance are given, so applying it in a real-time system is not straightforward. This holds for most non-real-time memory controllers.  ... 
doi:10.1109/codes-isss.2013.6658989 dblp:conf/codes/GoossensKAG13 fatcat:pu2ayhcuincm5emgjb3h36cpoa

Real-time visual tracking system modelling in MPSoC using platform based design

Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández, Nasser Kehtarnavaz, Matthias F. Carlsohn
2009 Real-Time Image and Video Processing 2009  
In this paper, we present the modelling of a real-time tracking system on a Multi-Processor System on Chip (MPSoC).  ...  Finally, the tracking system performance mapped onto the proposed architecture and shared resource usage were analyzed to determine the real architecture capacity, and also to find out possible bottlenecks  ...  ACKNOWLEDGEMENT This research is funded by the Spanish Ministry for Science and Technology, grant AP2006-02986, and Spanish Ministry for Science and Innovation, grant TEC2006-13599-C02.  ... 
doi:10.1117/12.811332 dblp:conf/rivp/JiaBNGH09 fatcat:u5is336ftnc7naqjfxfnl3mplq

Design space exploration for partially reconfigurable architectures in real-time systems

François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini
2013 Journal of systems architecture  
In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints,  ...  The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical  ...  Acknowledgements This work was carried out in the framework of project ARDMAHN [23] sponsored by the French National Research Agency, which aims at developing methodologies for home gateways integrating  ... 
doi:10.1016/j.sysarc.2013.06.007 fatcat:dixe4ecqyrce7prltrqkvrxaze

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems

Michel Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola Celanovic, Srinivas Devadas
2011 2011 IEEE 32nd Real-Time Systems Symposium  
This approach yields real-time execution on the order of 1μs simulation time step (including input/output latency) for a broad class of power electronics converters.  ...  The more extensive use of computation, sensing, and communication, tightly coupled with power processing, calls for a fundamental reassessment of some of the prevailing paradigms in the real-time control  ...  This is one of the earliest examples of an advanced, reconfigurable, real-time scientific computational machine that later came to be known as MIT's Differential Analyzer [2] .  ... 
doi:10.1109/rtss.2011.35 dblp:conf/rtss/KinsyKCMCD11 fatcat:p5g4mwqlcbgpvovedevvjpqtyq

Agent-based reconfigurable architecture for real-time object tracking

Yan Meng
2009 Journal of Real-Time Image Processing  
However, the real-time performance is hard to achieve due to the inherent characteristics of the sequential processing of these processors.  ...  Extensive experimental results of object tracking demonstrate that the proposed architecture is efficient and highly robust with real-time performance.  ...  In other words, it only depends on the real-time performance requirement of the interested problem. 4.  ... 
doi:10.1007/s11554-009-0116-2 fatcat:4ilih6xu3zcmfcgv5tm4keuuiq

Run-time energy management of manycore systems through reconfigurable interconnects

Jie Meng, Chao Chen, Ayse Kivilcim Coskun, Ajay Joshi
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
The active on-chip network channel width has a direct impact on the cache and memory access latency in manycore processors.  ...  This paper proposes a novel, low-cost method to reconfigure the network channel width at run time to maximize energy efficiency of applications.  ...  The core architecture is based on the cores used in the Intel single-chip cloud [16] . We assume shared memory programming model.  ... 
doi:10.1145/1973009.1973019 dblp:conf/glvlsi/MengCCJ11 fatcat:y2nlu5v7lzdjfglf26zxk5gde4

A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection

Kenta Takagi, Kosuke Mizuno, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 2013 IEEE International Conference on Acoustics, Speech and Signal Processing  
In this paper, a Histogram of Oriented Gradients (HOG) feature extraction accelerator for real-time multiple object detection is presented.  ...  Early classification reduces the number of computations in SVM classification.  ...  ACKNOWLEDGMENTS The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with STARC, e-Shuttle  ... 
doi:10.1109/icassp.2013.6638112 dblp:conf/icassp/TakagiMIKY13 fatcat:vd56qmxe3zapbk2nnl3qbclni4

Is time predictability quantifiable?

Martin Schoeberl
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
Computer architects and researchers in the realtime domain start to investigate processors and architectures optimized for real-time systems.  ...  Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time.  ...  A first simulation of their PRET architecture is presented in [12] .  ... 
doi:10.1109/samos.2012.6404196 dblp:conf/samos/Schoeberl12 fatcat:44rhizvp3fdtbi4ajif5xv6bz4

Run-time support for dynamically reconfigurable computing systems

Martyn Edwards, Peter Green
2003 Journal of systems architecture  
The reconfigurable computing devices like field programmable gate arrays have already been playing a vital role in the enhancement of the existing technology but still reconfigurable computing is suffering  ...  Reconfigurable computing is becoming an integral part of emerging scientific research since last few decades.  ...  On the other side a programmable real estate to build a separate computational unit for processor has an overhead which is manifest in time each of newly demanded different function, the central space  ... 
doi:10.1016/s1383-7621(03)00068-7 fatcat:weqgn7zw6ndcpggtkwcfcgtj44
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