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Simple and efficient approach for shunt admittance parameters calculations of VLSI on-chip interconnects on semiconducting substrate

H. Ymeri, B. Nauwelaers, K. Maex, D. De Roest, M. Stucchi, S. Vandenberghe
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition  
Conclusion We have presented a point matching method and cosine Fourier series approach for shunt admittance parameter calculation of coplanar interconnect lines on lossy silicon substrate based on the  ...  lines, that does not involve iterations and yields solutions of sufficient accuracy for most practical interconnections as used in common VLSI chips.  ...  Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate  ... 
doi:10.1109/date.2002.998468 dblp:conf/date/YmeriNMRSV02 fatcat:slj3pgx6inf5ff5nq2ndr5obhu

CAD-oriented equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate

Ji Zheng, Yeon-Chang Hahm, V.K. Tripathi, A. Weisshaar
2000 IEEE transactions on microwave theory and techniques  
A new, comprehensive CAD-oriented modeling methodology for single and coupled interconnects on an Si-SiO 2 substrate is presented.  ...  Index Terms-Coplanar strip line, equivalent circuit, interconnects, microstrip line, on-chip interconnects, silicon substrate, skin effect, spectral domain approach, SPICE model.  ...  QUASI-STATIC CHARACTERIZATION OF INTERCONNECTS ON A LOSSY SUBSTRATE The per unit length (p.u.l.) shunt admittance components , and series impedance counterparts , of single and coupled on-chip interconnects  ... 
doi:10.1109/22.868993 fatcat:bomszypu4je6xh3mo4ae6ohp24

Computation of Conductance and Capacitance for IC Interconnects on a General Lossy Multilayer Substrate

H. Ymeri, B. Nauwelaers, Karen Maex
2001 Active and Passive Electronic Components  
In this paper a simple method for analysis and modelling of transmission interconnect lines on general lossy multilayer substrates at high bit rates is presented.  ...  A discussion of the calculated line admittance in terms of technological and geometrical parameters of the structure is given.  ...  A simple 2-D procedure based on the multilayer spatial Green's function has been presented for the efficient calculation of the admittance per unit length of multilayered IC interconnects taking into account  ... 
doi:10.1155/2001/87589 fatcat:mov34qt3ivbt7bdsudtnrxoxpq

TiO2 Nanotube Arrays: Growth and Application [chapter]

Karthik Shankar
2016 Encyclopedia of Nanotechnology  
spectrum of science, ranging from physics and materials science to biology and biomedicine [1].  ...  These excitations, called surface plasmons (SPs), are determined by the long-range nature of the Coulomb interaction among electrons in metals and show a well-defined frequency/wave vector dispersion described  ...  On-chip wireless interconnects were demonstrated first for clock signal distribution at 15 GHz carrier frequency [19] .  ... 
doi:10.1007/978-94-017-9780-1_382 fatcat:i4ptwbhegbaana43geg7knhrda

Third-Generation Vectors [chapter]

2016 Encyclopedia of Nanotechnology  
spectrum of science, ranging from physics and materials science to biology and biomedicine [1].  ...  These excitations, called surface plasmons (SPs), are determined by the long-range nature of the Coulomb interaction among electrons in metals and show a well-defined frequency/wave vector dispersion described  ...  On-chip wireless interconnects were demonstrated first for clock signal distribution at 15 GHz carrier frequency [19] .  ... 
doi:10.1007/978-94-017-9780-1_101133 fatcat:m5haeiboy5ghzo3ksea3ijwuzu

SAW duplexer for PCS in US with excellent temperature stability

M. Kadota, T. Nakao, N. Taniguchi, E. Takata, M. Mimura, K. Nishiyama, T. Hada, T. Komura
IEEE Symposium on Ultrasonics, 2003  
Some of Rayleigh waves on various substrates have a good temperature characteristics, but almost all of their electromechanical coupling factor are too small for the US-PCS.  ...  Using the developed approaches, four QCM Miller oscillators of high sensibility for their use in damping media were implemented and characterized experimentally.  ...  The authors would like to acknowledge the financial support of Office of Naval Research (ONR)  ... 
doi:10.1109/ultsym.2003.1293335 fatcat:4qjft7omg5ehtgeokl6exvag4u

Transmission lines on integrated circuits for high speed communication

William Scott Lee
2012
, the equation becomes Z 0 = Z c nJ^ (4.6) 31 Combining the series impedance and shunt admittance of each block and calling them z and y results in z = jwL + R (4.1) y = j wC + G (4 .2) Starting with one  ...  z = juL + R (4.1) y = jcuC + G (4.2) Starting with one block with an impedance of Z c , a second block can be added in series with it by combining the shunt admittance, y, in parallel with Z t . and then  ... 
doi:10.26053/0h-8qqf-xdg0 fatcat:xokeelaptzco3jn7nf5vsefo2m

Design & Performance Comparison of FIR Low Pass Filter Using Kaiser Window & Remez Exchange Algorithm

Asst Nirav, Raghajibhai Patel, Asst Nirav, Raghajibhai Patel
2013 International Journal of Emerging Trends in Electrical and Electronics   unpublished
Depending on the response of the system, digital filters can be classified into Finite Impulse Exchange Algorithm produces most efficient filter with minimum possible order.  ...  This particular algorithm tremendously reduces the number of multipliers and adders.  ...  For the processing module various parameters i.e. speed, clock period, chip area (no. of slices used), power dissipation and combinational delay are compared.  ... 
fatcat:4tqrl3eqcfe6xb6mul3ys6qdli

DOTTORATO DI RICERCA IN TECNOLOGIE DELL'INFORMAZIONE Ciclo XXIV ADVANCED CMOS INTERFACES FOR BIO-NANOSENSORS Advanced CMOS interfaces for bio-nanosensors

Marco Crescentini, Coordinatore Dottorato, Relatore Chiar, Claudio Mo, Marco Fiegna, Tartagni
2012 unpublished
Their use in lab-on-a-chip could gives rise to new opportunities in many fields, from health-care and bio-warfare to environmental and high-throughput screening for pharmaceutical industry.  ...  It is based on a band-pass delta-sigma technique and combines low-noise performance with low-power requirements. As in the previous case, one CMOS chip has been realized.  ...  Acknowledgements First of all, I would like to thank my research advisor Prof. Marco Tartagni, for his support and encouragement during my Ph.D. course.  ... 
fatcat:cc4mnc6pk5e7doofzhq5esy7sm