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Photonic network-on-chip architecture using 3D integration

Aleksandr Biberman, Nicolás Sherwood-Droz, Xiaoliang Zhu, Kyle Preston, Gilbert Hendry, Jacob S. Levy, Johnnie Chan, Howard Wang, Michal Lipson, Keren Bergman, Louay A. Eldada, El-Hang Lee
2011 Optoelectronic Integrated Circuits XIII  
silicon photonics for advanced photonic NoCs.  ...  Furthermore, by leveraging deposited materials, we propose a novel fully-integrated scalable photonic switch architecture for data center networks, sustaining nonblocking 256×256 port size with nanosecond-scale  ...  CONCLUSIONS We have presented a powerful technique for realizing high-performance multi-layer silicon photonics, with devices methodically scalable to enable unprecedented performance in advanced photonic  ... 
doi:10.1117/12.880152 fatcat:acq5fbyfcjbb7l626esqmnky5m

Designing multi-socket systems using silicon photonics

Scott Beamer, Krste Asanović, Christopher Batten, Ajay Joshi, Vladimir Stojanović
2009 Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09  
Energy efficient off-chip silicon photonics could be used to deliver the needed bandwidth, and it could be extended on-chip to create a relatively flat network topology.  ...  Future single-board multi-socket systems may be unable to deliver the needed memory bandwidth electrically due to power limitations, which will hurt their ability to drive performance improvements.  ...  ARCHITECTURE For this research we target single-board multi-socket systems, and our design leverages the potential of photonics to produce a flat network.  ... 
doi:10.1145/1542275.1542360 dblp:conf/ics/BeamerABJS09 fatcat:ee3774av4rdm5knwx7kig3tmya

OIL

Duo Ding, David Z. Pan
2009 Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09  
under a new holistic photonic Networks-on-Chip architecture.  ...  In this paper, we present OIL, a parameterized Optical Interconnect Library of silicon nano-photonic devices for system level interconnect planning/analysis and low power high performance design exploration  ...  A HOLISTIC PHOTONIC NETWORK-ON-CHIP Network-on-Chip related architectures arose as a special class of applications for chip multi-processor communication efficiency, where high speed electrical wires are  ... 
doi:10.1145/1572471.1572475 dblp:conf/slip/DingP09 fatcat:qcayeyu3cnevfliwmbcfgnqhuy

Optical interconnection networks for high-performance computing systems

Aleksandr Biberman, Keren Bergman
2012 Reports on progress in physics (Print)  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1088/0034-4885/75/4/046402 pmid:22790508 fatcat:3nyeayt7l5di3grpw6mgjt4znq

Reports on progress in physics

L. R.
1962 Nuclear Physics  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1016/0029-5582(62)90796-4 fatcat:mggxvkfgcfapvmo4gb6m5z2fcq

Reports on progress in physics

1964 Nuclear Physics  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1016/0029-5582(64)90291-3 fatcat:nukswtihqvemrnmtfvttv2plya

Reports on Progress in Physics

1939 Nature  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1038/143833a0 fatcat:xc7y6mpxqrdhllrt35twxj6hye

Reports on Progress in Physics

1936 Nature  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1038/137597a0 fatcat:zelvhihbrbbctbi5dnxhdcdaua

Reports on Progress in Physics

1968 Physics Bulletin  
Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption.  ...  We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks.  ...  An example photonic network-on-chip topology that may be leveraged in these architectures is depicted in figure 1 . We have investigated many photonic network-on-chip architectures.  ... 
doi:10.1088/0031-9112/19/10/015 fatcat:zwgqqotpo5bznfnqonk4diu4te

LumiNOC

Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo
2012 Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12  
We propose a novel nano-photonic NoC architecture, LumiNOC, optimized for high performance and power-efficiency.  ...  To meet energy-efficient performance demands, the computing industry has moved to parallel computer architectures, such as chip-multi-processors (CMPs), internally interconnected via networks-on-chip (  ...  POWER EFFICIENCY IN PNOCS Power efficiency is an important motivation for photonic on-chip interconnect.  ... 
doi:10.1145/2370816.2370876 dblp:conf/IEEEpact/LiBGP12 fatcat:d57qb5kik5hnzaoe5o263mwxvm

Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors [chapter]

Cheng Li, Paul V. Gratz, Samuel Palermo
2015 More than Moore Technologies for Next Generation Computer Design  
Gratz, and Samuel Palermo systems makes traditional electrical on-chip networks prohibitive for future transformative extrascale computers.  ...  Third, our photonic network architecture leverages the same wavelengths for channel arbitration and parallel data transmission, allowing efficient utilization of the photonic resources and lowering static  ...  Power Efficiency in PNoCs Power efficiency is an important motivation for photonic on-chip interconnect.  ... 
doi:10.1007/978-1-4939-2163-8_7 fatcat:a46olb47unbxrgov5rcknn7sly

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program)

Madeleine Glick, Nathan Abrams, Qixiang Cheng, Min Yee Teh, Yu-Han Hung, Oscar Jimenez, Songtao Liu, Yoshitomo Okawachi, Michal Lipson, Alexander Gaeta, Keren Bergman, Leif Johansson (+7 others)
2020 Journal of Optical Communications and Networking  
The PINE program leverages the unique features of photonic technologies to enable alternative megadatacenters and high-performance computing (HPC) system architectures that deliver more substantial energy  ...  We review the motivation, goals, and achievements of the Photonic Integrated Networked Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects Agency-Energy (ARPA-E)  ...  However, given that the interconnect accounts for 15%-25% of the total system power, the opportunity for system efficiency improvements is limited if photonics is treated strictly as a more efficient "  ... 
doi:10.1364/jocn.402788 fatcat:evcrlkdyjfeunoy6fhh7aagjdy

Front Matter: Volume 9753

2016 Optical Interconnects XVI  
using a Base 36 numbering system employing both numerals and letters.  ...  Publication of record for individual papers is online in the SPIE Digital Library. SPIEDigitalLibrary.org Paper Numbering: Proceedings of SPIE follow an e-First publication model.  ...  integrated photonic interconnection technology for flexible data-centric optical networks (Invited Paper) [9753-29] 9753 0W High-performance flat data center network architecture based on scalable  ... 
doi:10.1117/12.2240147 fatcat:mj2vdgduq5bcraeki7t3syjhmi

Survey on Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Priyanka Rajendran, Dr.Gnana Sheela K
2014 IOSR Journal of VLSI and Signal processing  
As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores.  ...  This paper presents unified inter/intrachip optical network called UNION, for chip multiprocessors (CMPs). UNION is based on recent progresses in nanophotonic technologies.  ...  The interchip network connects all intrachip networks. for interchip communications. though bus-based communication architecture has limited scalability, it is still a viable low-cost choice for systems  ... 
doi:10.9790/4200-04615261 fatcat:ckatiqftd5db5h4ug5b2zlsbra

Balanced computing with nanophotonic interconnects

S. J. Ben Yoo, V. Akella, R. Amirtharajah, B. Baas, K. Bergman, S. Fan, J. S. Harris, M. Lipson, D. A. B. Miller, J. Shalf
2008 LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society  
We discuss low power and high productivity computing enabled by nanophotonic interconnects on chip.  ...  Amdahl's law suggests that a system with balanced computation and communications perform the best under most circumstance--a 10 Teraflop chip would require an interconnect bandwidth of 100 Tb/s.  ...  CMOS-compatible silicon photonics offer a practical platform for routing and transporting multi-wavelength optical signals interconnecting electronic processors and memories using the same CMOS fabrication  ... 
doi:10.1109/leos.2008.4688643 fatcat:dijqacmsffc35etf2ffboamkfu
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