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Dark silicon as a challenge for hardware/software co-design
2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis - CODES '14
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Dark Silicon refers to the observation that in future technology nodes, it may only be possible to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache blocks and so ...
In other words, chips will have an abundance of transistors, i.e., more than the number that can be simultaneously powered-on. ...
The switch-over between network layers is an important design requirement for our darkNoC architecture. ...
doi:10.1145/2656075.2661645
dblp:conf/codes/ShafiqueGMPH14
fatcat:jzmyheg2y5gphezfbblnvyzluq
Editorial: Networks on chips
2009
IET Computers & Digital Techniques
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Editorial Networks on chips Networking has been proven in the computer system arena to be an extremely effective means of managing parallel communication flows in distributed systems. ...
Moreover, guiding principles for the design of basic network building blocks (switches and network interfaces) are consolidated. ...
In 'Bandwidth Aware Routing Algorithms for Networks-on-Chip Platforms', authors M. Palesi, S. Kumar and V. Catania propose an embodiment of this approach. ...
doi:10.1049/iet-cdt.2009.9039
fatcat:u7ijbpjsvnfxzb3rtskmtf7bpa
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
2009
2009 International Conference on Complex, Intelligent and Software Intensive Systems
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for these systems, borrowed from the domain of off-chip interconnection networks. ...
However, the on-chip integration has to deal with unique challenges at different levels of abstraction. ...
The 2D mesh is currently the most popular regular topology used for on-chip networks in tilebased architectures, because it perfectly matches the 2D silicon surface. ...
doi:10.1109/cisis.2009.30
dblp:conf/cisis/VillamonLMBBG09
fatcat:ebynnnt4pzg7voy7o32dmfbbee
Special issue of International Journal of Electronics on evolutionary synthesis of network-on-chip-based systems
2010
International journal of electronics (Print)
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Network-on-chip (NoC) is an emerging paradigm for communications within large very-large-scale integrated (VLSI) systems implemented on a single silicon chip. ...
In the second paper, entitled 'Power-aware multi-objective evolutionary optimisation for application mapping on NoC platforms', the authors propose an innovative power-aware multi-objective evolutionary ...
doi:10.1080/00207217.2010.514128
fatcat:26o4i4rrlzgqvcpeqo6jjmb3ky
OIL
2009
Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09
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under a new holistic photonic Networks-on-Chip architecture. ...
Such an architecture incorporates on-chip packet routing (photonic Network-on-Chip) and with-in core wire routing (photonic waveguide routing) onto a dedicated optical layer, contributing towards enhanced ...
proposed Photonic Networkon-Chip architecture on SOI; (c) our proposed New Photonic Networks-on-Chip architecture combining (b) and within-core optical routing scenarios onto a dedicated photonic silicon ...
doi:10.1145/1572471.1572475
dblp:conf/slip/DingP09
fatcat:qcayeyu3cnevfliwmbcfgnqhuy
Silicon Nanophotonic Network-on-Chip Using TDM Arbitration
2010
2010 18th IEEE Symposium on High Performance Interconnects
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Silicon nanophotonics is an emerging technology platform for offering high-bandwidth connectivity with extreme energy efficiency for future networks-on-chip. ...
and other photonic network architectures. ...
aware of how the switch should be set. ...
doi:10.1109/hoti.2010.12
dblp:conf/hoti/HendryCKOSCB10
fatcat:kjfcufuebngq3b4oykeweoqn2e
The Green Data Center
2015
Zenodo
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A presentation given on the 2nd Green Photonics Symposium in Berlin March 2015. ...
Demands
Central control: Power Management via Analysis of Network Load "Elastic Tree" [3]
Distributed algorithm: "Power-aware fat-tree networks using on/off links" [4]
• Switches automatically ...
Silvera, "A Stable Network-Aware VM Placement for Cloud Systems," Ccgrid 2012. ...
doi:10.5281/zenodo.32795
fatcat:23unf5vaoff6zn6otcydjzwala
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Proceedings of the Third International Workshop on Network on Chip Architectures - NoCArc '10
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The gap between the constraints driving the design of onchip vs. off-chip interconnection networks (and hence the gap between the final network architectures selected for use in each domain) is increasingly ...
However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. ...
In fact, topologies for on-chip networks must match the 2D silicon surface, while off-chip realizations are dictated by board/rack organization. ...
doi:10.1145/1921249.1921259
dblp:conf/micro/LudoviciGVGB10
fatcat:xdpsu2mqi5gahgir43c4za5suq
A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
2008
Journal of Low Power Electronics
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Comparing to alternative solutions, the proposed one reduces the percentage of silicon area that operates under high power by 63%, while it leads to energy savings (about 9%), with an almost negligible ...
Since power consumption is a critical challenge for implementing applications onto reconfigurable hardware, a novel power-aware placement and routing (P&R) algorithm targeting to 3D FPGAs, is introduced ...
However, the feature for handling the spatial distribution of switched capacitance, results to a more balanced profile of power consumption sources, and hence to smaller gradient of the on-chip temperature ...
doi:10.1166/jolpe.2008.184
fatcat:4zfwqemj5rdz5bxkjmgf4za4be
Multi-layer adaptive power management architecture for TSV 3DIC applications
2013
2013 IEEE 63rd Electronic Components and Technology Conference
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The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips. ...
Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. ...
Meanwhile, the proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips. ...
doi:10.1109/ectc.2013.6575724
fatcat:stlqkvfaarehpkcopcrlkmdgpa
Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors
2011
Journal of Parallel and Distributed Computing
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Silicon nanophotonics as an interconnect technology offers several promising benefits for future networks-on-chip, including low end-to-end transmission energy and high bandwidth density of waveguides ...
In this work, we propose the use of time-divisionmultiplexed distributed arbitration in a photonic mesh network composed of silicon micro-ring resonator based photonic switches, which provides round-robin ...
Network implementation
Photonic switch
Switch controller In the proposed network architecture, each switch is controlled by a local controller which is aware of the current TDM slot by tracking ticks ...
doi:10.1016/j.jpdc.2010.09.009
fatcat:ekb3tejktbe3jot2e7qrnmxxc4
Jupiter rising
2016
Communications of the ACM
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First, multi-stage Clos topologies built from commodity switch silicon can support cost-effective deployment of buildingscale networks. ...
We built a centralized control mechanism based on a global configuration pushed to all datacenter switches. ...
(CE), Network Architecture and Operations (NetOps), Global Infrastructure Group (GIG), and Site Reliability Engineering (SRE) teams, to name a few. ...
doi:10.1145/2975159
fatcat:a4fmx3i5hnfldd2w7jqsodk7re
An overview about Networks-on-Chip with multicast suppor
[article]
2016
arXiv
pre-print
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Network-on-Chip (NoC) arises as a solution to interconnect these systems, which provides a scalable, reusable, and an efficient interconnect. ...
Modern System-on-Chip (SoC) platforms typically consist of multiple processors and a communication interconnect between them. ...
The algorithm adapted by [5] was implemented on a circuit switching Network-on-Chip. ...
arXiv:1610.00751v1
fatcat:rysfjplkcndtho2d4wa7664hwq
A Review of the Design Challenges for the 3-D on Chip Network Paradigms
2017
International Journal of Computer Applications
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The upcoming decades will require a change from mere transistor scaling to novel packaging architectures such as the vertical integration of chips referred as 3D integration. 3D silicon integration technologies ...
have provided new opportunities for NoC architecture design in SoCs enabling the design of complex and highly interconnected systems in reduced space providing higher efficiency compared to 2D integration ...
clock and power distribution networks for 3D ICs. ...
doi:10.5120/ijca2017914875
fatcat:c7wzcnumq5ca3evxthiourc66m
Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC)
2011
Journal of Parallel and Distributed Computing
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The first paper in the special section is "RAFT: A Router Architecture with Frequency Tuning for On-chip Networks", by ...
It is with great pleasure that we introduce the special issue on Networks-on-Chip (NoC) to the readers of the Journal of Parallel and Distributed Computing (JPDC). ...
The second paper is ''Time-Division-Multiplexed Arbitration in Silicon Nanophotonic Networks-On-Chip for High-Performance Chip Multiprocessors'', by Gilbert Hendry, Eric Robinson, Vitaliy Gleyzer, Johnnie ...
doi:10.1016/j.jpdc.2011.01.010
fatcat:cvaue5ynnbajxir6lzvr5z5eya
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